公开(公告)号：US20210124527A1

公开(公告)日：2021-04-29

申请号：US16892574

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G06F3/06 ,  G06F13/16 ,  G05D1/00

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.

公开(公告)号：US20240258180A1

公开(公告)日：2024-08-01

申请号：US18518114

申请日：2023-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehong Kwon ,  Daeseok Byeon

IPC: H01L21/66 ,  H01L23/00 ,  H01L23/48 ,  H01L23/528 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L22/30 ,  H01L23/481 ,  H01L23/528 ,  H01L24/08 ,  H01L25/0657 ,  H10B80/00 ,  H01L2224/08145

Abstract: A semiconductor device includes a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip, wherein a type of the second semiconductor chip is different from a type of the first semiconductor chip; and a crack detection circuit including: a first crack detection line repeatedly passing through an interface between the first semiconductor chip and the second semiconductor chip; a second crack detection line including a bonding pad or a through-via structure contacting a surface of the second semiconductor chip opposite to the interface; and a crack detector in the second semiconductor chip, the crack detector being configured to output a first test signal to the first crack detection line, receive a first reception signal from the first crack detection line, output a second test signal to the second crack detection line, and receive a second reception signal from the second crack detection line.

公开(公告)号：US11513730B2

公开(公告)日：2022-11-29

申请号：US16892574

申请日：2020-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G06F11/00 ,  G06F3/06 ,  G05D1/00 ,  G06F13/16 ,  G11C5/02 ,  B60W50/00

Abstract: A memory device includes a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data according to an M-bit data access scheme, where N is a natural number, and a first peripheral circuit for controlling the first memory cells and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data according to an M-bit data access scheme, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells and disposed below the second memory cell array, the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight.

公开(公告)号：US11264082B2

公开(公告)日：2022-03-01

申请号：US17024267

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G11C11/40 ,  G11C11/4091 ,  G11C11/4093 ,  G11C5/02 ,  G11C5/06 ,  G11C11/408

Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US20210125659A1

公开(公告)日：2021-04-29

申请号：US17024267

申请日：2020-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Daeseok Byeon ,  Chanho Kim ,  Taehyo Kim

IPC: G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093 ,  G11C11/408

Abstract: A memory device comprises a first memory area including a first memory cell array having a plurality of first memory cells each for storing N-bit data, where N is a natural number, and a first peripheral circuit for controlling the first memory cells according to an N-bit data access scheme and disposed below the first memory cell array, a second memory area including a second memory cell array having a plurality of second memory cells each for storing M-bit data, where M is a natural number greater than N, and a second peripheral circuit for controlling the second memory cells according to an M-bit data access scheme and disposed below the second memory cell array, wherein the first memory area and the second memory area are included in a single semiconductor chip and share an input and output interface, and a controller configured to generate calculation data by applying a weight stored in the first memory area to sensing data in response to receiving the sensing data obtained by an external sensor, and store the calculation data in one of the first memory area or the second memory area according to the weight, wherein the plurality of first memory cells and the plurality of second memory cells are included in a first chip having a first metal pad, the first peripheral circuit and the second peripheral circuit are included in a second chip having a second metal pad, and the first chip and the second chip are vertically connected to each other by the first metal pad and the second metal pad.

公开(公告)号：US11289467B2

公开(公告)日：2022-03-29

申请号：US16944711

申请日：2020-07-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Youngsun Min ,  Daeseok Byeon ,  Kyunghwa Yun

IPC: G11C5/06 ,  H01L25/18 ,  H01L23/00 ,  H01L25/065 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/14 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A memory device includes a memory cell array, a row decoder connected to the memory cell array by a plurality of string selection lines, a plurality of word lines, and a plurality of ground selection lines, and a common source line driver connected to the memory cell array by a common source line. The memory cell array is located in an upper chip, at least a portion of the row decoder is located in a lower chip, at least a portion of the common source line driver is located in the upper chip, and a plurality of upper bonding pads of the upper chip are connected to a plurality of lower bonding pads of the lower chip to connect the upper chip to the lower chip.

公开(公告)号：US11282851B2

公开(公告)日：2022-03-22

申请号：US16662073

申请日：2019-10-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehong Kwon ,  Chanho Kim ,  Daeseok Byeon ,  Pansuk Kwak ,  Chiweon Yoon

IPC: H01L27/11573 ,  H01L23/522 ,  H01L27/1157 ,  H01L29/78 ,  H01L29/94 ,  H01L27/11582

Abstract: A non-volatile memory device includes a substrate, a memory cell string including a vertical channel structure and memory cells, a voltage generator including a first transistor and configured to provide various voltages to the memory cells, and a vertical capacitor structure. The vertical capacitor structure includes first and second active patterns apart from each other in a first horizontal direction, a first gate pattern located above a channel region between the first and second active patterns, a first gate insulating film between the first gate pattern and the substrate in a vertical direction, and capacitor electrodes each extending in the vertical direction. The first transistor includes a second gate pattern and a second gate insulating film between the second gate pattern and the substrate in the vertical direction. The first gate insulating film has a thickness greater than a thickness of the second gate insulating film in the vertical direction.

公开(公告)号：US11237983B2

公开(公告)日：2022-02-01

申请号：US16865580

申请日：2020-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehyo Kim ,  Daeseok Byeon ,  Taehong Kwon ,  Chanho Kim ,  Taeyun Lee

IPC: G06F12/02 ,  G06F12/123 ,  G11C11/4091 ,  G11C11/408 ,  G11C11/4094 ,  G06F12/14

Abstract: A memory device includes; a memory area including a first memory area including first memory cells storing N-bit data and a second memory area including second memory cells storing M-bit data, where ‘M’ and ‘N’ are natural numbers and M is greater than N, and a controller configured to read data stored in the first memory area using a first read operation, read data stored in the second memory area using a second read operation different from the first read operation, and selectively store data in one of the first memory area and the second memory area based on a frequency of use (FOU) of the data.

公开(公告)号：US20240296898A1

公开(公告)日：2024-09-05

申请号：US18399018

申请日：2023-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taehong Kwon ,  Daeseok Byeon

IPC: G11C29/12

CPC classification number: G11C29/12005 ,  G11C29/12015 ,  G11C2029/1202

Abstract: A memory device includes a memory cell array connected to a plurality of word lines, a clock generator configured to generate a clock signal, a charge pump circuit configured to generate a voltage to be provided to the plurality of word lines, based on the clock signal, a row decoder configured to provide the voltage to a selected memory block, a current generation circuit connected in parallel to a word line path through which the voltage is provided from the charge pump circuit to the row decoder and configured to generate a current flowing through the word line path for a reference time, and a defect detection circuit configured to detect a defect on the word line path by comparing a first count value of the clock signal counted before the reference time with a second count value of the clock signal counted after the reference time.

公开(公告)号：US20240145306A1

公开(公告)日：2024-05-02

申请号：US18236165

申请日：2023-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyosoo CHOO ,  Daeseok Byeon ,  Taehong Kwon

IPC: H01L21/78 ,  H01L23/00 ,  H10B43/27

CPC classification number: H01L21/78 ,  H01L24/80 ,  H01L24/94 ,  H10B43/27 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2224/94

Abstract: A method of manufacturing a semiconductor device is provided. The method includes: forming a first structure on a first wafer; forming a second structure on a second wafer including second chip regions and a second scribe lane region surrounding the second chip regions; separating first ones of the second chip regions in a central portion of the second wafer in a plan view by a first dicing process; bonding the first ones of the second chip regions with the first wafer; separating second ones of the second chip regions in an edge portion of the second wafer in a plan view by a second dicing process; bonding the second ones of the second chip regions with the first wafer, and separating the bonded first and second wafers by a third dicing process.