公开(公告)号：US20220114317A1

公开(公告)日：2022-04-14

申请号：US17465361

申请日：2021-09-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Wang ,  Woosung Choi

IPC: G06F30/367 ,  G06N3/08

Abstract: A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing training data comprising input state values and training capacitance values to a neural network executing on a computer system; processing the input state values through the neural network to generate modeled charge values; converting the modeled charge values to modeled capacitance values; determining, by the computer system, whether the training capacitance values of the training data are within a threshold value of the modeled capacitance values utilizing a loss function that omits the modeled charge values; and in response to determining that the training capacitance values of the training data are within the threshold value of the modeled capacitance values, converting, by the computer system, the neural network to a circuit simulation code to generate a converted neural network.

公开(公告)号：US20200320366A1

公开(公告)日：2020-10-08

申请号：US16430219

申请日：2019-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Wang ,  Woosung Choi

IPC: G06N3/04 ,  G06F17/50 ,  G06N3/08

Abstract: A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.

公开(公告)号：US20190265296A1

公开(公告)日：2019-08-29

申请号：US16406868

申请日：2019-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: G01R31/317 ,  G01R31/3193 ,  G01R31/3177

Abstract: In a method of circuit yield analysis, the method includes: detecting a plurality of failed samples respectively located at a plurality of failure regions in a multi-dimensional parametric space; clustering the failed samples to identify the failure regions; filtering features of the failed samples to determine a parameter component that is a non-principal component in affecting circuit yield; applying a dimensional reduction method on a dimension corresponding to the parameter component; and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions containing a rare failure event.

公开(公告)号：US20180075179A1

公开(公告)日：2018-03-15

申请号：US15344346

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Wang ,  Nuo Xu ,  Woosung Choi

IPC: G06F17/50 ,  H01L29/423 ,  H01L29/06 ,  H01L29/45 ,  H01L27/02

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F2217/06 ,  H01L27/0207 ,  H01L29/0657 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/78

Abstract: A method for selecting transistor design parameters. A first set of simulations is used to calculate leakage current at a plurality of sets of design parameter values, and the results are fitted with a first response surface methodology model. The first model is used to generate a function that returns a value of a selected design parameter, for which a leakage current specification is just met. A second set of simulations is used to calculate effective drive current for a plurality of sets of design parameter values, and the results are fitted with a second response surface methodology model. The second model is used, together with the first, to search for a set of design parameter values at which a worst-case effective drive current is greatest, subject to the constraint of meeting the worst-case leakage current specification.

公开(公告)号：US20180074124A1

公开(公告)日：2018-03-15

申请号：US15365808

申请日：2016-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31718 ,  G01R31/2894 ,  G01R31/3177

Abstract: A method of circuit yield analysis for evaluating rare failure events existing in multiple disjoint failure regions defined by a multi-dimensional parametric space, the method including performing initial sampling to detect failed samples respectively located at multiple failure regions in the multi-dimensional parametric space, performing clustering to identify the failure regions, performing feature filtering to determine which parameter component is a non-principal component in affecting circuit yield, applying a dimensional reduction method on a dimension corresponding to the parameter component, optimizing an importance sampling (IS) distribution function corresponding to each of the failure regions, and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions.

公开(公告)号：US20210351270A1

公开(公告)日：2021-11-11

申请号：US16900788

申请日：2020-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Hyun Park ,  Zhengping Jiang ,  Hesameddin Ilatikhameneh ,  Woosung Choi ,  Chihak Ahn

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78

Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.

公开(公告)号：US10330727B2

公开(公告)日：2019-06-25

申请号：US15365808

申请日：2016-11-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3193 ,  G01R31/34

Abstract: A method of circuit yield analysis for evaluating rare failure events existing in multiple disjoint failure regions defined by a multi-dimensional parametric space, the method including performing initial sampling to detect failed samples respectively located at multiple failure regions in the multi-dimensional parametric space, performing clustering to identify the failure regions, performing feature filtering to determine which parameter component is a non-principal component in affecting circuit yield, applying a dimensional reduction method on a dimension corresponding to the parameter component, optimizing an importance sampling (IS) distribution function corresponding to each of the failure regions, and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions.

公开(公告)号：US20190155971A1

公开(公告)日：2019-05-23

申请号：US15875916

申请日：2018-01-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chihak Ahn ,  Woosung Choi

IPC: G06F17/50

Abstract: A system and method for calculating stress in a device includes receiving an analytic solution domain and calculating initial analytic values for displacement and stress for a dislocation in the domain and creating a stress profile using the initial displacement and the initial stress as initial values of a stress equilibration equation.

公开(公告)号：US20190138897A1

公开(公告)日：2019-05-09

申请号：US15951052

申请日：2018-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Zhengping Jiang ,  Weiyi Qi ,  Jing Wang ,  Woosung Choi

IPC: G06N3/08 ,  G06F17/50

Abstract: According to one embodiment of the present invention a circuit simulator configured to simulate a degraded output of a circuit including a plurality of transistors includes: a behavioral recurrent neural network configured to receive an input waveform and to compute a circuit output waveform; a feature engine configured to model one or more degraded circuit elements in accordance with an aging time, to receive the circuit output waveform and to output a plurality of degraded features; and a physics recurrent neural network configured to receive the plurality of degraded features from the feature engine and to simulate the degraded output of the circuit.

公开(公告)号：US10204188B2

公开(公告)日：2019-02-12

申请号：US14991124

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Wang ,  Nuo Xu ,  Woosung Choi

IPC: G06F17/50

Abstract: A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing a technology computer aided design data set corresponding to nominal performance of the semiconductor device, identifying a plurality of process variation sources that correspond to process variations that occur during the manufacturing of the semiconductor device, generating a nominal value look-up table of electrical parameters of the semiconductor device using nominal values of each of the plurality of process variation sources, and generating a plurality of process variation look-up tables of electrical parameters of the semiconductor device using variation values corresponding to each of the plurality of process variation sources that are identified as corresponding to the semiconductor device.