公开(公告)号：US20190096659A1

公开(公告)日：2019-03-28

申请号：US16107942

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Fan Chen ,  Weiyi Qi ,  Jongchol Kim ,  Jing Wang ,  Yang Lu ,  Woosung Choi

IPC: H01L21/02 ,  G06F9/30 ,  G06N3/08

Abstract: A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.

公开(公告)号：US10069013B2

公开(公告)日：2018-09-04

申请号：US15358822

申请日：2016-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: H03F3/187 ,  H01L29/786 ,  H03F1/02 ,  H03F3/45 ,  A61B5/0482 ,  H01L29/66 ,  H01L29/78 ,  H01L29/739 ,  H01L29/165

Abstract: Neural signal amplifiers include an operational amplifier and a feedback network coupled between an output and an input thereof. The feedback network includes a tunnel field effect transistor (“TFET”) pseudo resistor that exhibits bi-directional conductivity. A drain region of the TFET may be electrically connected to the gate electrode thereof to provide a bi-directional resistor having good symmetry in terms of resistance as a function of voltage polarity.

公开(公告)号：US11003737B2

公开(公告)日：2021-05-11

申请号：US15696150

申请日：2017-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Zhengping Jiang ,  Woosung Choi

IPC: G06F17/18 ,  G01R31/28 ,  G06F17/14 ,  G06F7/62 ,  G01R31/317

Abstract: A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

公开(公告)号：US20180300288A1

公开(公告)日：2018-10-18

申请号：US15696150

申请日：2017-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Zhengping Jiang ,  Woosung Choi

IPC: G06F17/18 ,  G06F17/14 ,  G01R31/28

Abstract: A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

公开(公告)号：US20160267205A1

公开(公告)日：2016-09-15

申请号：US14991124

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Wang ,  Nuo Xu ,  Woosung Choi

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F17/5036 ,  G06F17/5081 ,  G06F2217/10

Abstract: A computer implemented method for determining performance of a semiconductor device is provided. The method includes providing a technology computer aided design data set corresponding to nominal performance of the semiconductor device, identifying a plurality of process variation sources that correspond to process variations that occur during the manufacturing of the semiconductor device, generating a nominal value look-up table of electrical parameters of the semiconductor device using nominal values of each of the plurality of process variation sources, and generating a plurality of process variation look-up tables of electrical parameters of the semiconductor device using variation values corresponding to each of the plurality of process variation sources that are identified as corresponding to the semiconductor device.

Abstract translation: 提供了一种用于确定半导体器件性能的计算机实现方法。 该方法包括提供对应于半导体器件的标称性能的技术计算机辅助设计数据集，识别对应于在制造半导体器件期间发生的工艺变化的多个工艺变化源，产生标称值查找表 使用所述多个处理变化源中的每一个的标称值来使用所述半导体器件的电参数，以及使用对应于所述多个工艺变化中的每一个的变化值来生成所述半导体器件的电参数的多个工艺变化查找表 被识别为对应于半导体器件的源。

公开(公告)号：US11282695B2

公开(公告)日：2022-03-22

申请号：US16107942

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Fan Chen ,  Weiyi Qi ,  Jongchol Kim ,  Jing Wang ,  Yang Lu ,  Woosung Choi

IPC: H01L21/02 ,  G06N3/08 ,  G06F9/30 ,  G06N3/04 ,  G06N3/12

Abstract: A system for reconstructing wafer maps of semiconductor wafers includes: a processor; and memory having instructions stored thereon that, when executed by the processor, cause the processor to: receive test data of a wafer at sparse sampling locations of the wafer, the sparse sampling locations being selected based on a probing mask; and compute a reconstructed wafer map by performing compressed sensing with Zernike polynomials on the test data at sparse locations of the wafer.

公开(公告)号：US09728639B2

公开(公告)日：2017-08-08

申请号：US14642918

申请日：2015-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/66 ,  H01L21/265 ,  H01L29/06 ,  H01L29/165 ,  H01L29/739 ,  H01L21/28 ,  H01L29/49

CPC classification number: H01L29/7848 ,  H01L21/26513 ,  H01L21/28035 ,  H01L29/0688 ,  H01L29/0834 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/4916 ,  H01L29/66356 ,  H01L29/66636 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7843 ,  H01L29/7845

Abstract: Tunnel field effect transistors include a semiconductor substrate; a source region in the semiconductor substrate; a drain region in the semiconductor substrate; a channel region in the semiconductor substrate between the source region and the drain region; and a gate electrode on the semiconductor substrate above the channel region. The source region comprises a first region having a first conductivity type, a third region having a second conductivity type that is different from the first conductivity type, and a second region having an intrinsic conductivity type that is between the first region and the third region.

公开(公告)号：US09526436B2

公开(公告)日：2016-12-27

申请号：US14729339

申请日：2015-06-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: H03F3/187 ,  A61B5/0482 ,  H03F1/02 ,  H03F3/45

CPC classification number: H01L29/78624 ,  A61B5/0482 ,  H01L29/165 ,  H01L29/66356 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/7843 ,  H01L29/7845 ,  H03F1/0205 ,  H03F3/45179 ,  H03F3/45475 ,  H03F2203/45116 ,  H03F2203/45118 ,  H03F2203/45288

Abstract: Neural signal amplifiers include an operational amplifier and a feedback network coupled between an output and an input thereof. The feedback network includes a tunnel field effect transistor (“TFET”) pseudo resistor that exhibits bi-directional conductivity. A drain region of the TFET may be electrically connected to the gate electrode thereof to provide a bi-directional resistor having good symmetry in terms of resistance as a function of voltage polarity.

Abstract translation: 神经信号放大器包括耦合在输出端和输入端之间的运算放大器和反馈网络。 反馈网络包括呈现双向导电性的隧道场效应晶体管（“TFET”）伪电阻器。 TFET的漏极区域可以电连接到其栅电极，以提供作为电压极性的函数的电阻方面具有良好对称性的双向电阻器。

公开(公告)号：US20190265296A1

公开(公告)日：2019-08-29

申请号：US16406868

申请日：2019-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Woosung Choi

IPC: G01R31/317 ,  G01R31/3193 ,  G01R31/3177

Abstract: In a method of circuit yield analysis, the method includes: detecting a plurality of failed samples respectively located at a plurality of failure regions in a multi-dimensional parametric space; clustering the failed samples to identify the failure regions; filtering features of the failed samples to determine a parameter component that is a non-principal component in affecting circuit yield; applying a dimensional reduction method on a dimension corresponding to the parameter component; and constructing a final importance sampling (IS) distribution function using a mixed Gaussian (mGaussian) function corresponding to all of the failure regions containing a rare failure event.

公开(公告)号：US20180075179A1

公开(公告)日：2018-03-15

申请号：US15344346

申请日：2016-11-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jing Wang ,  Nuo Xu ,  Woosung Choi

IPC: G06F17/50 ,  H01L29/423 ,  H01L29/06 ,  H01L29/45 ,  H01L27/02

CPC classification number: G06F17/5036 ,  G06F17/5045 ,  G06F2217/06 ,  H01L27/0207 ,  H01L29/0657 ,  H01L29/42376 ,  H01L29/456 ,  H01L29/78

Abstract: A method for selecting transistor design parameters. A first set of simulations is used to calculate leakage current at a plurality of sets of design parameter values, and the results are fitted with a first response surface methodology model. The first model is used to generate a function that returns a value of a selected design parameter, for which a leakage current specification is just met. A second set of simulations is used to calculate effective drive current for a plurality of sets of design parameter values, and the results are fitted with a second response surface methodology model. The second model is used, together with the first, to search for a set of design parameter values at which a worst-case effective drive current is greatest, subject to the constraint of meeting the worst-case leakage current specification.