公开(公告)号：US20210351270A1

公开(公告)日：2021-11-11

申请号：US16900788

申请日：2020-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Hyun Park ,  Zhengping Jiang ,  Hesameddin Ilatikhameneh ,  Woosung Choi ,  Chihak Ahn

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/423 ,  H01L29/78

Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.

公开(公告)号：US20190138897A1

公开(公告)日：2019-05-09

申请号：US15951052

申请日：2018-04-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Zhengping Jiang ,  Weiyi Qi ,  Jing Wang ,  Woosung Choi

IPC: G06N3/08 ,  G06F17/50

Abstract: According to one embodiment of the present invention a circuit simulator configured to simulate a degraded output of a circuit including a plurality of transistors includes: a behavioral recurrent neural network configured to receive an input waveform and to compute a circuit output waveform; a feature engine configured to model one or more degraded circuit elements in accordance with an aging time, to receive the circuit output waveform and to output a plurality of degraded features; and a physics recurrent neural network configured to receive the plurality of degraded features from the feature engine and to simulate the degraded output of the circuit.

公开(公告)号：US11171211B1

公开(公告)日：2021-11-09

申请号：US16900788

申请日：2020-06-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hong-Hyun Park ,  Zhengping Jiang ,  Hesameddin Ilatikhameneh ,  Woosung Choi ,  Chihak Ahn

IPC: H01L29/10 ,  H01L29/08 ,  H01L21/02 ,  H01L29/04 ,  H01L29/66

Abstract: A method of manufacturing a p-type MOSFET includes depositing a channel material to form a channel region, forming a source region and a drain region on each side of the channel region along a first direction, depositing a gate oxide layer on the channel region along a second direction crossing the first direction, and depositing a gate electrode on the gate oxide. The channel material includes a group IV element or III-V semiconductor compound and have a diamond or zincblende cubic crystal structure. A direction of the crystal structure is parallel to the second direction. Two adjacent atoms on an out-most atomic layer of the channel region along the first direction are connected to each other via a single intervening atom, and an interface between the gate oxide layer and the channel region has a surface roughness of 1 angstrom or lower.

公开(公告)号：US11003737B2

公开(公告)日：2021-05-11

申请号：US15696150

申请日：2017-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Zhengping Jiang ,  Woosung Choi

IPC: G06F17/18 ,  G01R31/28 ,  G06F17/14 ,  G06F7/62 ,  G01R31/317

Abstract: A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.

公开(公告)号：US20180300288A1

公开(公告)日：2018-10-18

申请号：US15696150

申请日：2017-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nuo Xu ,  Jing Wang ,  Zhengping Jiang ,  Woosung Choi

IPC: G06F17/18 ,  G06F17/14 ,  G01R31/28

Abstract: A method of circuit yield analysis for evaluating rare failure events includes performing initial sampling to detect failed samples respectively located at one or more failure regions in a multi-dimensional parametric space, generating a distribution of failed samples at discrete values along each dimension, identifying the failed samples, performing a transform to project the failed samples into all dimensions in a transform space, and classifying a type of failure region for each dimension in the parametric space.