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11.发明申请公开(公告)号：US20250104748A1
公开(公告)日：2025-03-27
申请号：US18971939
申请日：2024-12-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung CHO , Min Hwi KIM , Ji-Sang LEE
Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.
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公开(公告)号：US20240161790A1
公开(公告)日：2024-05-16
申请号：US18203754
申请日：2023-05-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jaehue SHIN , Yongsung CHO , Daeseok BYEON
CPC classification number: G11C7/1057 , G11C5/14 , G11C7/1069 , G11C7/12
Abstract: A memory device includes a memory cell array including a plurality of memory cells, and a page buffer circuit including a plurality of page buffer units respectively connected with the memory cells through a plurality of bit lines. A sensing node is connected to a bit line for each buffer circuit. The plurality of page buffer units are respectively connected with sensing nodes, each of the plurality of page buffer units includes at least one transistor. One or more auxiliary wires in the proximity of the sensing node are used to reduce coupling problems caused by a low capacitance of the sensing node.
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