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公开(公告)号：US20180197610A1
公开(公告)日：2018-07-12
申请号：US15661386
申请日：2017-07-27
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Sang LEE
CPC classification number: G11C16/10 , G11C7/22 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C2029/0411
Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
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2.发明公开公开(公告)号：US20230386539A1
公开(公告)日：2023-11-30
申请号：US18449864
申请日：2023-08-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung CHO , Min Hwi KIM , Ji-Sang LEE
CPC classification number: G11C7/20 , G11C7/065 , G11C7/1039 , G11C7/12
Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.
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公开(公告)号：US20200350019A1
公开(公告)日：2020-11-05
申请号：US16934150
申请日：2020-07-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Sang LEE
Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
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公开(公告)号：US20180090216A1
公开(公告)日：2018-03-29
申请号：US15493326
申请日：2017-04-21
Applicant: Samsung Electronics Co., Ltd.
Inventor： Wook-Ghee HAHN , Ji-Sang LEE
CPC classification number: G11C16/3427 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3459 , G11C16/349 , G11C2211/563 , H01L27/11582
Abstract: In a method of reading data in a nonvolatile memory device including a plurality of memory cells arranged at intersections of a plurality of word-lines and a plurality of bit-lines, a read request on a first word-line of the plurality of word-lines is received, a read operation is performed on a second word-line adjacent to the first word-line and a read operation is performed on the first word-line based on data read from memory cells of the second word-line. The read operation on the first word-line is performed by adjusting a level of recover read voltage applied to the first word-line during the read operation of the first word-line based on at least one of a program state of the data read from memory cells of the second word-line and an operating parameter of the nonvolatile memory device.
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公开(公告)号：US20250118370A1
公开(公告)日：2025-04-10
申请号：US18986889
申请日：2024-12-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Sang LEE
Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
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Patent Agency Ranking
6.发明申请公开(公告)号：US20230060080A1
公开(公告)日：2023-02-23
申请号：US17888661
申请日：2022-08-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung CHO , Min Hwi KIM , Ji-Sang LEE
Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.
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公开(公告)号：US20210375366A1
公开(公告)日：2021-12-02
申请号：US17402955
申请日：2021-08-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Sang LEE
Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
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8.发明申请公开(公告)号：US20250104748A1
公开(公告)日：2025-03-27
申请号：US18971939
申请日：2024-12-06
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yongsung CHO , Min Hwi KIM , Ji-Sang LEE
Abstract: Disclosed is a memory device which includes a memory cell array including memory cells, data latches connected with a sensing node and storing data in a first memory cell of the memory cells, a sensing latch connected with the sensing node, a temporary storage node, a switch connected between the sensing latch and the temporary storage node and configured to operate in response to a temporary storage node setup signal, a first precharge circuit configured to selectively precharge a first bit line corresponding to the first memory cell depending on a level of the temporary storage node, and a control logic circuit configured to control a dump operation between the data latches, the sensing latch, and the temporary storage node. The control logic circuit performs the dump operation from the data latches to the sensing latch while the first precharge circuit selectively precharges the first bit line.
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公开(公告)号：US20240046991A1
公开(公告)日：2024-02-08
申请号：US18491966
申请日：2023-10-23
Applicant: Samsung Electronics Co., Ltd.
Inventor： Ji-Sang LEE
CPC classification number: G11C16/10 , G11C16/08 , G11C16/24 , G11C16/0483 , G11C16/26 , G11C16/32 , G11C16/3459 , G11C7/22
Abstract: A non-volatile memory device includes: a memory cell array including a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to selectively control the plurality of word lines, a page buffer including a plurality of latches corresponding to the plurality of bit lines, respectively, and a control circuit configured to control the non-volatile memory device to enter a suspend state after terminating a verify operation of a program loop of a program operation of the plurality of memory cells in response to a suspend request being generated during an execution operation of the program loop.
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公开(公告)号：US20130250696A1
公开(公告)日：2013-09-26
申请号：US13872379
申请日：2013-04-29
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ji-Sang LEE
IPC: G11C16/04
CPC classification number: G11C16/04 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/26 , G11C16/28 , G11C16/3454 , G11C2211/5621
Abstract: A method of programming a nonvolatile memory device comprises programming target memory cells among a plurality of memory cells connected to a wordline, performing a first sensing operation on the plurality of memory cells, and selectively performing a second sensing operation on the target memory cells based on a result of the first sensing operation.
Abstract translation: 一种对非易失性存储器件进行编程的方法包括在连接到字线的多个存储器单元中编程目标存储器单元，对所述多个存储器单元执行第一感测操作，并且基于所述目标存储器单元选择性地对所述目标存储器单元执行第二感测操作 这是第一感测操作的结果。
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