公开(公告)号：US20240096820A1

公开(公告)日：2024-03-21

申请号：US18334100

申请日：2023-06-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Young Lyong KIM ,  Hyun Soo CHUNG ,  In Hyo HWANG

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/16 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065 ,  H10B80/00

CPC classification number: H01L23/562 ,  H01L21/563 ,  H01L23/16 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/5383 ,  H01L23/5385 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/50 ,  H10B80/00 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204

Abstract: A method for manufacturing a semiconductor package includes mounting semiconductor chips on an interposer, forming a molding part between the semiconductor chips, surrounding a plurality of bumps between the semiconductor chips and the interposer with a first underfill, forming a sacrificial layer that covers the semiconductor chips, forming a wafer level molding layer that covers the sacrificial layer, performing a planarization process to expose upper sides of the semiconductor chips, form the sacrificial layer into a sacrificial pattern, and form the wafer level molding layer into a wafer level molding pattern, removing the sacrificial pattern, performing a sawing process to remove an outer edge of the semiconductor package, mounting the interposer on a side of a package board, surrounding a plurality of bumps between the package board and the interposer with a second underfill, and attaching a stiffener to an outer portion of the package board.

公开(公告)号：US20230035026A1

公开(公告)日：2023-02-02

申请号：US17712358

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young Lyong KIM ,  Hyunsoo CHUNG

IPC: H01L23/00 ,  H01L25/065 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor chip on a package substrate, a second semiconductor chip on the first semiconductor chip and having a redistribution layer on a bottom surface thereof, under-bump pads on a bottom surface of the redistribution layer, first solders adjacent to the first semiconductor chip and connecting first pads of the under-bump pads to substrate pads of the package substrate, and a molding layer on the package substrate and covering the first and second semiconductor chips and the first solders. Second pads of the under-bump pads are in direct contact with a top surface of the first semiconductor chip. The first pads are connected through the redistribution layer to an integrated circuit of the second semiconductor chip. The second pads are insulated from the integrated circuit of the second semiconductor chip.