公开(公告)号：US20200012924A1

公开(公告)日：2020-01-09

申请号：US16180462

申请日：2018-11-05

Applicant: SanDisk Technologies LLC

Inventor： Wen Ma ,  Minghai Qin ,  Won Ho Choi ,  Pi-Feng Chiu ,  Martin Van Lueker-Boden

IPC: G06N3/063 ,  G06N5/04 ,  G06N99/00

Abstract: Enhanced techniques and circuitry are presented herein for artificial neural networks. These artificial neural networks are formed from artificial neurons, which in the implementations herein comprise a memory array having non-volatile memory elements. Neural connections among the artificial neurons are formed by interconnect circuitry coupled to input control lines and output control lines of the memory array to subdivide the memory array into a plurality of layers of the artificial neural network. Control circuitry is configured to transmit a plurality of iterations of an input value on input control lines of a first layer of the artificial neural network for inference operations by at least one or more additional layers. The control circuitry is also configured to apply an averaging function across output values successively presented on output control lines of a last layer of the artificial neural network from each iteration of the input value.

公开(公告)号：US20210326110A1

公开(公告)日：2021-10-21

申请号：US16850395

申请日：2020-04-16

Applicant: SanDisk Technologies LLC

Inventor： Wen Ma ,  Pi-Feng Chiu ,  Won Ho Choi ,  Martin Lueker-Boden

IPC: G06F7/523 ,  G11C13/00

Abstract: Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node is used to configure the resolution. In one serial mode, the number of cycles over which a DAC provides voltages is used to configure the resolution. The memory system may include relatively low resolution voltage sources, which avoids the need to have complex high resolution voltage sources (e.g., high resolution DACs). Lower resolution voltage sources can take up less area and/or use less power than higher resolution voltage sources.

公开(公告)号：US20200311512A1

公开(公告)日：2020-10-01

申请号：US16901302

申请日：2020-06-15

Applicant: SanDisk Technologies LLC

Inventor： Won Ho Choi ,  Pi-Feng Chiu ,  Wen Ma ,  Minghai Qin ,  Gerrit Jan Hemink ,  Martin Lueker-Boden

IPC: G06N3/04 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16 ,  G06N3/08 ,  G06N3/063 ,  G11C16/04 ,  G11C16/26

Abstract: Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.