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    DIFFERENTIAL NON-VOLATILE MEMORY CELL FOR ARTIFICIAL NEURAL NETWORK
    2.
    发明申请
    DIFFERENTIAL NON-VOLATILE MEMORY CELL FOR ARTIFICIAL NEURAL NETWORK 审中-公开

    公开(公告)号：US20200034686A1

    公开(公告)日：2020-01-30

    申请号：US16405178

    申请日：2019-05-07

    Applicant: SanDisk Technologies LLC

    Inventor： Pi-Feng Chiu ,  Won Ho Choi ,  Wen Ma ,  Martin Lueker-Boden

    IPC: G06N3/04 ,  G11C11/56 ,  G11C13/00 ,  G11C11/16 ,  G06N3/08

    Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit.

    METHODS TO TOLERATE PROGRAMMING AND RETENTION ERRORS OF CROSSBAR MEMORY ARRAYS
    4.
    发明申请
    METHODS TO TOLERATE PROGRAMMING AND RETENTION ERRORS OF CROSSBAR MEMORY ARRAYS 有权

    公开(公告)号：US20210117500A1

    公开(公告)日：2021-04-22

    申请号：US16912717

    申请日：2020-06-26

    Applicant: SanDisk Technologies LLC

    Inventor： Minghai Qin ,  Pi-Feng Chiu ,  Wen Ma ,  Won Ho Choi

    IPC: G06F17/16 ,  G11C11/22 ,  G11C13/00 ,  G11C11/16

    Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

    METHODS TO TOLERATE PROGRAMMING AND RETENTION ERRORS OF CROSSBAR MEMORY ARRAYS
    6.
    发明申请
    METHODS TO TOLERATE PROGRAMMING AND RETENTION ERRORS OF CROSSBAR MEMORY ARRAYS 有权

    公开(公告)号：US20210117499A1

    公开(公告)日：2021-04-22

    申请号：US16655575

    申请日：2019-10-17

    Applicant: SanDisk Technologies LLC

    Inventor： Minghai Qin ,  Pi-Feng Chiu ,  Wen Ma ,  Won Ho Choi

    IPC: G06F17/16 ,  G11C11/22 ,  G11C11/16 ,  G11C13/00

    Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

    Methods to tolerate programming and retention errors of crossbar memory arrays
    8.
    发明授权
    Methods to tolerate programming and retention errors of crossbar memory arrays 有权

    公开(公告)号：US11556616B2

    公开(公告)日：2023-01-17

    申请号：US16655575

    申请日：2019-10-17

    Applicant: SanDisk Technologies LLC

    Inventor： Minghai Qin ,  Pi-Feng Chiu ,  Wen Ma ,  Won Ho Choi

    IPC: G06F17/16 ,  G11C11/22 ,  G11C11/16 ,  G11C13/00

    Abstract: Systems and methods for reducing the impact of defects within a crossbar memory array when performing multiplication operations in which multiple control lines are concurrently selected are described. A group of memory cells within the crossbar memory array may be controlled by a local word line that is controlled by a local word line gating unit that may be configured to prevent the local word line from being biased to a selected word line voltage during an operation; the local word line may instead be set to a disabling voltage during the operation such that the memory cell currents through the group of memory cells are eliminated. If a defect has caused a short within one of the memory cells of the group of memory cells, then the local word line gating unit may be programmed to hold the local word line at the disabling voltage during multiplication operations.

    Reconfigurable input precision in-memory computing
    9.
    发明授权
    Reconfigurable input precision in-memory computing 有权

    公开(公告)号：US11556311B2

    公开(公告)日：2023-01-17

    申请号：US16850395

    申请日：2020-04-16

    Applicant: SanDisk Technologies LLC

    Inventor： Wen Ma ,  Pi-Feng Chiu ,  Won Ho Choi ,  Martin Lueker-Boden

    IPC: G06F7/52 ,  G06F7/523 ,  G11C13/00 ,  G06N3/04

    Abstract: Technology for reconfigurable input precision in-memory computing is disclosed herein. Reconfigurable input precision allows the bit resolution of input data to be changed to meet the requirements of in-memory computing operations. Voltage sources (that may include DACs) provide voltages that represent input data to memory cell nodes. The resolution of the voltage sources may be reconfigured to change the precision of the input data. In one parallel mode, the number of DACs in a DAC node is used to configure the resolution. In one serial mode, the number of cycles over which a DAC provides voltages is used to configure the resolution. The memory system may include relatively low resolution voltage sources, which avoids the need to have complex high resolution voltage sources (e.g., high resolution DACs). Lower resolution voltage sources can take up less area and/or use less power than higher resolution voltage sources.

    CONFIGURABLE PRECISION NEURAL NETWORK WITH DIFFERENTIAL BINARY NON-VOLATILE MEMORY CELL STRUCTURE
    10.
    发明申请
    CONFIGURABLE PRECISION NEURAL NETWORK WITH DIFFERENTIAL BINARY NON-VOLATILE MEMORY CELL STRUCTURE 审中-公开

    公开(公告)号：US20200035305A1

    公开(公告)日：2020-01-30

    申请号：US16414143

    申请日：2019-05-16

    Applicant: SanDisk Technologies LLC

    Inventor： Won Ho Choi ,  Pi-Feng Chiu ,  Wen Ma ,  Martin Lueker-Boden

    IPC: G11C16/08 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08

    Abstract: Use of a non-volatile memory array architecture to realize a neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a neural network is formed by a differential memory cell of two individual memory cells, such as a memory cells having a programmable resistance, each connected between a corresponding one of a word line pair and a shared bit line. An input is applied as a pattern of voltage values on word line pairs connected to the unit synapses to perform the multiplication of the input with the weight by determining a voltage level on the shared bit line. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a summation circuit. The approach can be extended from binary weights to multi-bit weight values by use of multiple differential memory cells for a weight.

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