公开(公告)号：US08654873B2

公开(公告)日：2014-02-18

申请号：US13436092

申请日：2012-03-30

申请人： Gururaj Padaki ,  Sunil Hosur Rames ,  Rakesh A Joshi ,  Raghavendra Raichur ,  Rajendra Hegde

发明人： Gururaj Padaki ,  Sunil Hosur Rames ,  Rakesh A Joshi ,  Raghavendra Raichur ,  Rajendra Hegde

IPC分类号： H04K1/10

CPC分类号： H04N5/455 ,  H04L1/0054 ,  H04L1/0065 ,  H04L5/0048 ,  H04L25/03178 ,  H04L27/2656 ,  H04L27/2662 ,  H04L27/2666 ,  H04L27/2675 ,  H04N21/4382

摘要： In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC′ pattern to obtain a RS packet align boundary.

摘要翻译： 在一个实施例中，提供了一种使用一个或多个位去交织的偶数和奇数正交频分复用（OFDM）符号来执行在TV接收机中的维特比解码输入处使解调器同步的方法的电视（TV）接收机。 该方法包括：（i）当比特解交织的偶数和奇数OFDM符号不存在帧边界时，对比特解交织的偶数和奇数OFDM符号执行维特比解码，（ii）对经解码的偶数和奇数OFDM符号执行卷积编码 维特比解码的数据输出，（iii）确定比特解交织的OFDM符号的卷积编码的输出是否与维特比解码时的输入匹配，以及（iv）确定比特de的卷积编码的输出 交错的偶数和奇数OFDM符号与SYNC模式或SYNC'模式匹配以获得RS数据包对齐边界。

公开(公告)号：US20120249889A1

公开(公告)日：2012-10-04

申请号：US13436092

申请日：2012-03-30

申请人： Gururaj Padaki ,  Sunil Hosur Ramesh ,  Rakesh A. Joshi ,  Raghavendra Raichur ,  Rajendra Hegde

发明人： Gururaj Padaki ,  Sunil Hosur Ramesh ,  Rakesh A. Joshi ,  Raghavendra Raichur ,  Rajendra Hegde

IPC分类号： H04N5/455

CPC分类号： H04N5/455 ,  H04L1/0054 ,  H04L1/0065 ,  H04L5/0048 ,  H04L25/03178 ,  H04L27/2656 ,  H04L27/2662 ,  H04L27/2666 ,  H04L27/2675 ,  H04N21/4382

摘要： In one embodiment, a Television (TV) receiver to perform a method of synchronizing a demodulator at a Viterbi decode input in the TV receiver using one or more bit de-interleaved even and odd Orthogonal Frequency Division Multiplexing (OFDM) symbols is provided. The method includes (i) performing a Viterbi decoding on the bit de-interleaved even and odd OFDM symbols when a frame boundary does not exist for the bit de-interleaved even and odd OFDM symbols, (ii) performing a convolutional encoding on an decoded data output of the Viterbi decoding, (iii) determining whether an output of the convolutional encoding of the bit de-interleaved OFDM symbols matches an input at a Viterbi decode, and (iv) determining whether the output of the convolutional encoding of the bit de-interleaved even and odd OFDM symbols matches with a SYNC pattern or a SYNC′ pattern to obtain a RS packet align boundary.

摘要翻译： 在一个实施例中，提供了一种使用一个或多个位去交织的偶数和奇数正交频分复用（OFDM）符号来执行在TV接收机中的维特比解码输入处使解调器同步的方法的电视（TV）接收机。 该方法包括：（i）当比特解交织的偶数和奇数OFDM符号不存在帧边界时，对比特解交织的偶数和奇数OFDM符号执行维特比解码，（ii）对经解码的偶数和奇数OFDM符号执行卷积编码 维特比解码的数据输出，（iii）确定比特解交织的OFDM符号的卷积编码的输出是否与维特比解码时的输入匹配，以及（iv）确定比特de的卷积编码的输出 交错的偶数和奇数OFDM符号与SYNC模式或SYNC'模式匹配以获得RS数据包对齐边界。

公开(公告)号：US09092227B2

公开(公告)日：2015-07-28

申请号：US13462144

申请日：2012-05-02

申请人： Anindya Saha ,  Gururaj Padaki ,  Santosh Billava ,  Rakesh A. Joshi

发明人： Anindya Saha ,  Gururaj Padaki ,  Santosh Billava ,  Rakesh A. Joshi

IPC分类号： G06F15/76 ,  G06F9/302 ,  G06F9/38 ,  G06F9/30 ,  G06F7/58 ,  G06F15/80 ,  H04L25/03 ,  H04L27/00

CPC分类号： G06F9/3887 ,  G06F7/552 ,  G06F7/586 ,  G06F9/3001 ,  G06F9/30109 ,  G06F9/3893 ,  G06F15/8053 ,  G06F15/8076 ,  G06F2207/3828 ,  G06F2207/5523 ,  H04L25/03019 ,  H04L27/0008

摘要： A vector slot processor that is capable of supporting multiple signal processing operations for multiple demodulation standards is provided. The vector slot processor includes a plurality of micro execution slot (MES) that performs the multiple signal processing operations on the high speed streaming inputs. Each of the MES includes one or more n-way signal registers that receive the high speed streaming inputs, one or more n-way coefficient registers that store filter coefficients for the multiple signal processing, and one or more n-way Multiply and Accumulate (MAC) units that receive the high speed streaming inputs from the one or more n-way signal registers and filter coefficients from one or more n-way coefficient registers. The one or more n-way MAC units perform a vertical MAC operation and a horizontal multiply and add operation on the high speed streaming inputs.

摘要翻译： 提供了能够支持用于多个解调标准的多个信号处理操作的向量时隙处理器。 矢量时隙处理器包括对高速流输入进行多信号处理操作的多个微执行时隙（MES）。 每个MES包括接收高速流输入的一个或多个n路信号寄存器，存储多信号处理的滤波器系数的一个或多个n路系数寄存器和一个或多个n路乘法和累加（ MAC）单元，其从一个或多个n路信号寄存器接收高速流输入和来自一个或多个n路系数寄存器的滤波器系数。 一个或多个n路MAC单元在高速流输入上执行垂直MAC操作和水平乘法和相加操作。