公开(公告)号：US20190121740A1

公开(公告)日：2019-04-25

申请号：US15790297

申请日：2017-10-23

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Sidheshkumar Ramanlal Patel ,  Sneha Kishor Wagh

IPC: G06F12/0868 ,  G06F3/06 ,  G06F12/02 ,  G06F15/78 ,  G06F5/06 ,  G06F12/0873 ,  G06F12/1027 ,  G06F12/1009

Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

公开(公告)号：US20180348298A1

公开(公告)日：2018-12-06

申请号：US15611047

申请日：2017-06-01

Applicant: Seagate Technology LLC

Inventor： Rajesh Maruti Bhagwat ,  Nitin Satishchandra Kabra ,  Jay Shah

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31703 ,  G01R31/31723 ,  G01R31/318544 ,  G01R31/318563 ,  G01R31/318566

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

公开(公告)号：US20170329686A1

公开(公告)日：2017-11-16

申请号：US15154839

申请日：2016-05-13

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Rajesh Maruti Bhagwat ,  Nitin Satishchandra Kabra

IPC: G06F11/26 ,  G06F13/24 ,  G06F1/10

CPC classification number: G06F11/26 ,  G06F1/10 ,  G06F13/24

Abstract: Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.