公开(公告)号：US11630779B2

公开(公告)日：2023-04-18

申请号：US17528977

申请日：2021-11-17

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

IPC: G06F12/0873 ,  G06F12/128 ,  G06F12/02

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

公开(公告)号：US20190065404A1

公开(公告)日：2019-02-28

申请号：US15691193

申请日：2017-08-30

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Rajesh Maruti Bhagwat ,  Jackson Ellis ,  Geert Rosseel

IPC: G06F12/128 ,  G06F12/0897

Abstract: Implementations described and claimed herein provide a method and system for adaptive caching in a storage device. The method includes receiving an adaptive caching policy from a host for caching host read data and host write data in a hybrid drive using NAND cache, and allocating read cache for the host read data and write cache for the host write data in the NAND cache based on the adaptive caching policy. In some implementations, the method also includes iteratively performing an input/output (I/O) profiling operation to generate an I/O profile. An adaptive caching policy may be applied based on the I/O profile. When a unit time has completed, a new I/O profile may be compared with a current I/O profile. A new adaptive caching policy is applied based on determining the new I/O profile is different than the current I/O profile.

公开(公告)号：US20190339326A1

公开(公告)日：2019-11-07

申请号：US16511792

申请日：2019-07-15

Applicant: Seagate Technology LLC

Inventor： Rajesh Maruti Bhagwat ,  Nitin Satishchandra Kabra ,  Jay Shah

IPC: G01R31/3177 ,  G01R31/3185 ,  G01R31/317

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

公开(公告)号：US20180349040A1

公开(公告)日：2018-12-06

申请号：US15609651

申请日：2017-05-31

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

IPC: G06F3/06 ,  G06F12/128 ,  G06F12/0873

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

公开(公告)号：US10127126B2

公开(公告)日：2018-11-13

申请号：US15154839

申请日：2016-05-13

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Rajesh Maruti Bhagwat ,  Nitin Satishchandra Kabra

IPC: G06F11/00 ,  G06F11/26 ,  G06F1/10 ,  G06F13/24

Abstract: Systems and methods for improving system debugging using finite state machines are described. In one embodiment, the systems and methods includes selecting, by a first multiplexor, a period of a timer tick for one or more blocks of a system on a chip (SoC), comparing, by a first comparator, a current state of the one or more blocks to a previous state of the one or more blocks, and receiving, by a finite state machine (FSM), the result from the first comparator as a first input, receiving a pulse based on the selected period of the timer tick from the first multiplexor as a second input, and based on the first and second inputs generating an output indicating whether the current and previous states remain unchanged after a time of at least two timer ticks. In one embodiment, a result from the first comparator indicates whether the current state equals the previous state of the one or more blocks.

公开(公告)号：US11232037B2

公开(公告)日：2022-01-25

申请号：US15790297

申请日：2017-10-23

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Sidheshkumar Ramanlal Patel ,  Sneha Kishor Wagh

IPC: G06F12/0868 ,  G06F3/06 ,  G06F12/02 ,  G06F12/0873 ,  G06F12/1027

Abstract: A cache management mechanism is provided having a size that is independent of an overall storage capacity of a non-volatile memory (NVM). The cache management mechanism includes a first level map data structure arranged as a first-in-first-out (FIFO) buffer to list a plurality of host access commands sequentially received from a host device. Each command has an associated host tag value. A cache memory stores user data blocks associated with the commands. A second level map of the cache management mechanism correlates cache addresses with the host tag values. A processing core searches the FIFO buffer in an effort to match a logical address of an existing command to the logical address for a new command. If a match is found, the host tag value is used to locate the cache address for the requested data. If a cache miss occurs, the new command is forwarded to the NVM.

公开(公告)号：US11221956B2

公开(公告)日：2022-01-11

申请号：US15609651

申请日：2017-05-31

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

IPC: G06F12/0873 ,  G06F12/128 ,  G06F12/02

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

公开(公告)号：US10353001B2

公开(公告)日：2019-07-16

申请号：US15611047

申请日：2017-06-01

Applicant: Seagate Technology LLC

Inventor： Rajesh Maruti Bhagwat ,  Nitin Satishchandra Kabra ,  Jay Shah

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.

公开(公告)号：US20220075729A1

公开(公告)日：2022-03-10

申请号：US17528977

申请日：2021-11-17

Applicant: Seagate Technology LLC

Inventor： Nitin Satishchandra Kabra ,  Jackson Ellis ,  Niranjan Anant Pol ,  Mark Ish

IPC: G06F12/0873 ,  G06F12/128 ,  G06F12/02

Abstract: A hybrid storage device with three-level memory mapping is provided. An illustrative device comprises a primary storage device comprising a plurality of primary sub-blocks; a cache memory device comprising a plurality of cache sub-blocks implemented as a cache for the primary storage device; and a controller configured to map at least one portion of one or more primary sub-blocks of the primary storage device stored in the cache to a physical location in the cache memory device using at least one table identifying portions of the primary storage device that are cached in one or more of the cache sub-blocks of the cache memory device, wherein a size of the at least one table is independent of a capacity of the primary storage device.

公开(公告)号：US10921372B2

公开(公告)日：2021-02-16

申请号：US16511792

申请日：2019-07-15

Applicant: Seagate Technology LLC

Inventor： Rajesh Maruti Bhagwat ,  Nitin Satishchandra Kabra ,  Jay Shah

IPC: G01R31/28 ,  G01R31/3177 ,  G01R31/317 ,  G01R31/3185

Abstract: A method of testing an IC chip having a plurality of programmable blocks and at least one memory. The method includes configuring a first programmable block of the plurality of programmable blocks with scan test logic for carrying out a scan test on other ones of the plurality of programmable blocks. The method further includes generating scan patterns and expected results for the scan test outside the IC chip. The generated scan patterns and expected results are loaded into the memory. The scan patterns from the memory are injected into the other programmable blocks. An output response of the other programmable blocks to the scan patterns is obtained. The output response is compared with the expected results by the scan test logic within the first programmable block. A scan test result based on the comparison between the output response and the expected results is provided.