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公开(公告)号:US09525017B2
公开(公告)日:2016-12-20
申请号:US14848698
申请日:2015-09-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hideaki Shishido , Hiroyuki Miyake , Kouhei Toyotaka , Makoto Kaneyasu
IPC: H01L27/32
CPC classification number: H01L27/124 , G02F1/134309 , G02F1/134336 , G02F1/13624 , G02F1/136277 , G02F1/136286 , G02F2201/52 , G09G3/2085 , G09G3/3607 , G09G3/3611 , G09G3/3659 , G09G2300/0465 , G09G2300/08 , H01L27/1255 , H01L27/3211 , H01L27/3213 , H01L27/3216 , H01L27/3218 , H01L27/323 , H01L27/3244 , H01L27/3248 , H01L27/326 , H01L27/3262 , H01L27/3276 , H01L33/62
Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.
Abstract translation: 提供了具有高分辨率,高显示质量或高开口率的显示装置。 像素包括三个子像素,并且电连接到两个栅极线。 栅极线之一电连接到两个子像素中的每一个中包括的晶体管的栅极,另一个栅极线电连接到另一子像素中包括的晶体管的栅极。 三个子像素的显示元件被排列成相同的方向。 三个子像素的三个像素电极被布置在相同的方向上。
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公开(公告)号:US20160079333A1
公开(公告)日:2016-03-17
申请号:US14848698
申请日:2015-09-09
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hideaki Shishido , Hiroyuki Miyake , Kouhei Toyotaka , Makoto Kaneyasu
IPC: H01L27/32
CPC classification number: H01L27/124 , G02F1/134309 , G02F1/134336 , G02F1/13624 , G02F1/136277 , G02F1/136286 , G02F2201/52 , G09G3/2085 , G09G3/3607 , G09G3/3611 , G09G3/3659 , G09G2300/0465 , G09G2300/08 , H01L27/1255 , H01L27/3211 , H01L27/3213 , H01L27/3216 , H01L27/3218 , H01L27/323 , H01L27/3244 , H01L27/3248 , H01L27/326 , H01L27/3262 , H01L27/3276 , H01L33/62
Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.
Abstract translation: 提供了具有高分辨率,高显示质量或高开口率的显示装置。 像素包括三个子像素,并且电连接到两个栅极线。 栅极线之一电连接到两个子像素中的每一个中包括的晶体管的栅极,另一个栅极线电连接到另一子像素中包括的晶体管的栅极。 三个子像素的显示元件被排列成相同的方向。 三个子像素的三个像素电极被布置在相同的方向上。
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公开(公告)号:US10217772B2
公开(公告)日:2019-02-26
申请号:US15959566
申请日:2018-04-23
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hideaki Shishido , Hiroyuki Miyake , Kouhei Toyotaka , Makoto Kaneyasu
IPC: H01L27/12 , H01L27/32 , G02F1/1343 , G02F1/1362 , G09G3/36 , G09G3/20 , H01L33/62
Abstract: Provided is a display device with high resolution, high display quality, or high aperture ratio. A pixel includes three subpixels and is electrically connected to two gate lines. One of the gate lines is electrically connected to a gate of a transistor included in each of the two subpixels, and the other gate line is electrically connected to a gate of a transistor included in the other subpixel. Display elements of the three subpixels are arranged in the same direction. Three pixel electrodes of the three subpixels are arranged in the same direction.
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公开(公告)号:US20180047758A1
公开(公告)日:2018-02-15
申请号:US15792031
申请日:2017-10-24
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Makoto Kaneyasu
IPC: H01L27/12 , H01L29/786
CPC classification number: H01L27/1225 , G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2310/0262 , G09G2320/045 , H01L29/7869 , H01L29/78696
Abstract: To provide a light-emitting device capable of suppressing the display of an afterimage. A plurality of pixels arranged in n rows and m columns (n and m are each an integer of 2 or more) is supplied with a first signal containing image data and a second signal for initializing the pixels. Each pixel includes a first transistor for controlling the input of the first signal and a second transistor for controlling the input of the second signal. The first transistor in a k-th row (k is an integer of 1 to n) and the second transistor in a k+1-th row are turned on at the same time, so that the pixels are initialized and display images effectively.
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公开(公告)号:US09111483B2
公开(公告)日:2015-08-18
申请号:US13718402
申请日:2012-12-18
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hiroyuki Miyake , Kouhei Toyotaka , Kazunori Watanabe , Toru Tanabe , Makoto Kaneyasu , Masashi Fujita
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2370/08
Abstract: To provide a display device with high image quality and fewer terminals. The present invention is made with a focus on the positional relation between a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit. The structure conceived is such that a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit are provided close to each other so that an RC load between the serial-parallel conversion circuit and the external connection terminal is reduced.
Abstract translation: 提供具有高图像质量和较少终端的显示设备。 本发明的重点是串行并行转换电路和用于向串行 - 并行转换电路提供串行信号的外部连接端子之间的位置关系。 所构想的结构使得串行并行转换电路和用于向串行 - 并行转换电路提供串行信号的外部连接端子彼此靠近地设置,使得串行 - 并行转换电路和外部电路之间的RC负载 连接端子减少。
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公开(公告)号:US20130162609A1
公开(公告)日:2013-06-27
申请号:US13718402
申请日:2012-12-18
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hiroyuki Miyake , Kouhei Toyotaka , Kazunori Watanabe , Toru Tanabe , Makoto Kaneyasu , Masashi Fujita
IPC: G09G3/20
CPC classification number: G09G3/20 , G09G2370/08
Abstract: To provide a display device with high image quality and fewer terminals. The present invention is made with a focus on the positional relation between a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit. The structure conceived is such that a serial-parallel conversion circuit and an external connection terminal for supplying a serial signal to the serial-parallel conversion circuit are provided close to each other so that an RC load between the serial-parallel conversion circuit and the external connection terminal is reduced
Abstract translation: 提供具有高图像质量和更少终端的显示设备。 本发明的重点是串行并行转换电路和用于向串行 - 并行转换电路提供串行信号的外部连接端子之间的位置关系。 所构想的结构使得串行并行转换电路和用于向串行 - 并行转换电路提供串行信号的外部连接端子彼此靠近地设置,使得串行 - 并行转换电路和外部电路之间的RC负载 连接端子减少
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公开(公告)号:US11493808B2
公开(公告)日:2022-11-08
申请号:US17326675
申请日:2021-05-21
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hiroyuki Miyake , Makoto Kaneyasu
IPC: H01L29/10 , H01L29/12 , G02F1/1343 , G09F9/30 , G09G3/36 , H01L29/786 , H01L27/12 , G02F1/1362 , G02F1/136 , G02F1/13357
Abstract: A display device in which parasitic capacitance between wirings can be reduced is provided. Furthermore, a display device in which display quality is improved is provided. Furthermore, a display device in which power consumption can be reduced is provided.
The display device includes a signal line, a scan line, a first electrode, a second electrode, a third electrode, a first pixel electrode, a second pixel electrode, and a semiconductor film. The signal line intersects with the scan line, the first electrode is electrically connected to the signal line, the first electrode has a region overlapping with the scan line, the second electrode faces the first electrode, the third electrode faces the first electrode, the first pixel electrode is electrically connected to the second electrode, the second pixel electrode is electrically connected to the third electrode, the semiconductor film is in contact with the first electrode, the second electrode, and the third electrode, and the semiconductor film is provided between the scan line and the first electrode to the third electrode.-
公开(公告)号:US10651203B2
公开(公告)日:2020-05-12
申请号:US14732034
申请日:2015-06-05
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Makoto Kaneyasu
Abstract: To provide an input device and an input/output device with high detection sensitivity. The input device includes a first transistor, a second transistor, a capacitor, a node, a first wiring, a second wiring, a third wiring, and a fourth wiring. The first transistor includes a first gate and a second gate. The first and second gates of the first transistor overlap with each other with a semiconductor film therebetween. The second gate of the first transistor is electrically connected to the node. The first wiring is electrically connected to the second wiring through the first transistor. The third wiring is electrically connected to the node through the second transistor. A first terminal of the capacitor is electrically connected to the node, and a second terminal of the capacitor is electrically connected to the fourth wiring.
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公开(公告)号:US10139663B2
公开(公告)日:2018-11-27
申请号:US15153077
申请日:2016-05-12
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Hideaki Shishido , Koji Kusunoki , Kouhei Toyotaka , Kazunori Watanabe , Makoto Kaneyasu
IPC: G02F1/1335 , G02F1/1333 , G06F3/041 , G06F3/044 , G02F1/1362 , G02F1/1343
Abstract: An input/output device is provided. The input/output device includes a first pixel electrode, a second pixel electrode, a first common electrode, a second common electrode, a liquid crystal, a first insulating film, a second insulating film, and a transistor. The first common electrode can serve as one electrode of a sensor element. The second common electrode can serve as the other electrode of the sensor element. The transistor includes a first gate, a second gate, and a semiconductor layer. The pixel electrode, the common electrodes, and the second gate are positioned on different planes. The second gate contains one or more kinds of metal elements included in the semiconductor layer. The second gate, the pixel electrode, and the common electrodes preferably contain one or more kinds of metal elements included in the semiconductor layer.
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公开(公告)号:US09985052B2
公开(公告)日:2018-05-29
申请号:US15792031
申请日:2017-10-24
Applicant: Semiconductor Energy Laboratory Co., Ltd.
Inventor: Makoto Kaneyasu
IPC: H01L27/12 , G09G3/3233 , H01L29/786
CPC classification number: H01L27/1225 , G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2310/0262 , G09G2320/045 , H01L29/7869 , H01L29/78696
Abstract: To provide a light-emitting device capable of suppressing the display of an afterimage. A plurality of pixels arranged in n rows and m columns (n and m are each an integer of 2 or more) is supplied with a first signal containing image data and a second signal for initializing the pixels. Each pixel includes a first transistor for controlling the input of the first signal and a second transistor for controlling the input of the second signal. The first transistor in a k-th row (k is an integer of 1 to n) and the second transistor in a k+1-th row are turned on at the same time, so that the pixels are initialized and display images effectively.
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