公开(公告)号：US12039952B2

公开(公告)日：2024-07-16

申请号：US18134054

申请日：2023-04-13

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kouhei Toyotaka ,  Motoharu Saito

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3696 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/021

Abstract: A display apparatus which includes a driver with low power consumption and in which an output voltage of the driver is boosted by a pixel is provided. The source driver in which a logic unit and an amplifier unit operate appropriately by the same low voltage is included, and the pixel has a function of retaining first data, a function of adding second data to the first data to generate third data, and a function of supplying the third data to a display device. Thus, even when a voltage output from the source driver is low, the voltage can be boosted by the pixel; accordingly, the display device can operate appropriately.

公开(公告)号：US11955612B2

公开(公告)日：2024-04-09

申请号：US18093833

申请日：2023-01-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kazutaka Kuriki ,  Ryota Tajima ,  Kouhei Toyotaka ,  Hideaki Shishido ,  Toshiyuki Isa

IPC: H01M10/48 ,  G06N3/04 ,  G06N3/065 ,  H01M10/44 ,  H02J7/00

CPC classification number: H01M10/482 ,  G06N3/04 ,  G06N3/065 ,  H01M10/441 ,  H01M10/486 ,  H02J7/0013 ,  H02J7/0047 ,  H02J7/007

Abstract: A power storage system with excellent characteristics is provided. A power storage system with a high degree of safety is provided. A power storage system with less deterioration is provided. A storage battery with excellent characteristics is provided. The power storage system includes a neural network and a storage battery. The neural network includes an input layer, an output layer, and one or more hidden layers between the input layer and the output layer. The predetermined hidden layer is connected to the previous hidden layer or the previous input layer by a predetermined weight coefficient, and connected to the next hidden layer or the next output layer by a predetermined weight coefficient. In the storage battery, voltage and time at which the voltage is obtained are measured as one of sets of data. The sets of data measured at different times are input to the input layer and the operational condition of the storage battery is changed in accordance with a signal output from the output layer.

公开(公告)号：US11881177B2

公开(公告)日：2024-01-23

申请号：US17411205

申请日：2021-08-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hidetomo Kobayashi ,  Kouhei Toyotaka

IPC: G09G3/3266 ,  G09G3/34 ,  G09G3/36 ,  G09G3/3233 ,  H10K59/121

CPC classification number: G09G3/3266 ,  G09G3/3233 ,  G09G3/3426 ,  G09G3/3648 ,  G09G2300/023 ,  G09G2300/046 ,  G09G2300/0426 ,  G09G2300/0439 ,  G09G2300/0456 ,  G09G2300/0809 ,  G09G2300/0842 ,  G09G2310/0286 ,  H10K59/1213

Abstract: A display device that can be easily and more flexibly designed is provided. The display device includes a pixel circuit and a driver circuit in a display portion. The driver circuit includes a plurality of pulse output circuits. Each of the plurality of pulse output circuits has a function of driving a gate line. The pixel circuit is electrically connected to the gate line. Each of the plurality of pulse output circuits includes a first transistor. The pixel circuit includes a second transistor. A layer including the second transistor is over a layer including the first transistor, and the first transistor and the second transistor overlap with each other.

公开(公告)号：US11817698B2

公开(公告)日：2023-11-14

申请号：US17256667

申请日：2019-06-25

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei Takahashi ,  Koji Kusunoki ,  Kouhei Toyotaka ,  Kazunori Watanabe

IPC: H02J7/00 ,  G01R31/396 ,  G01R31/3835 ,  H01L29/786

CPC classification number: H02J7/007182 ,  G01R31/3835 ,  G01R31/396 ,  H02J7/0048 ,  H01L29/7869

Abstract: A battery management circuit with a novel structure and a power storage device including the battery management circuit are provided. The power storage device includes a plurality of battery cells connected in series and a battery management circuit. The battery management circuit includes a voltage monitor circuit having a function of acquiring a voltage value between a pair of electrodes of any one of the battery cells. The voltage monitor circuit includes a multiplexer and a buffer circuit for outputting a signal for controlling the multiplexer. The multiplexer and the buffer circuit each include an n-channel transistor. The n-channel transistor is a transistor including an oxide semiconductor in a channel formation region. The multiplexer has a function of retaining an output voltage of the battery cell by setting the transistor in an off state.

公开(公告)号：US11562675B2

公开(公告)日：2023-01-24

申请号：US17269736

申请日：2019-09-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kouhei Toyotaka ,  Kazunori Watanabe ,  Susumu Kawashima ,  Daisuke Kubota ,  Tetsuji Ishitani ,  Akio Yamashita

IPC: G09G3/20 ,  G06F3/041

Abstract: A flip-flop circuit is provided. A driver circuit is provided. The flip-flop circuit includes first to fifth input terminals and first to third output terminals, the first input terminal is supplied with a first trigger signal, the second input terminal is supplied with a second trigger signal, the third input terminal is supplied with a batch selection signal, the fourth input terminal is supplied with a first pulse width modulation signal, and the fifth input terminal is supplied with a second pulse width modulation signal. The first output terminal supplies a first selection signal in response to the first pulse width modulation signal in a period from supply of the first trigger signal to supply of the second trigger signal, the first output terminal supplies the first selection signal in a period during which the batch selection signal is supplied, the second output terminal supplies a second selection signal in response to the second pulse width modulation signal in the period from the supply of the first trigger signal to the supply of the second trigger signal, and the third output terminal supplies a third trigger signal.

公开(公告)号：US11508307B2

公开(公告)日：2022-11-22

申请号：US17273818

申请日：2019-08-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei Takahashi ,  Koji Kusunoki ,  Kouhei Toyotaka ,  Susumu Kawashima ,  Kazunori Watanabe

IPC: G09G3/3258 ,  H01L25/16 ,  H01L27/32

Abstract: A display device that can correct the threshold voltage of a driving transistor without a correction of image data is provided. A display device including a pixel provided with a driving transistor, a display element, and a memory circuit and a correction data generation circuit is related. One of a source and a drain of the driving transistor is electrically connected to one electrode of the display element, and a gate of the driving transistor is electrically connected to the memory circuit. In a first period, the correction data generation circuit generates correction data that is data for correcting the threshold voltage of the driving transistor. In a second period, first data is written to the memory circuit. In a third period, second data is supplied to the pixel, whereby third data in which the second data is added to the first data is generated. In a fourth period, an image corresponding to the third data is displayed by the display element.

公开(公告)号：US11075255B2

公开(公告)日：2021-07-27

申请号：US15854067

申请日：2017-12-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kouhei Toyotaka ,  Kei Takahashi ,  Hideaki Shishido ,  Shunpei Yamazaki

IPC: H01L27/32 ,  H01L27/02 ,  H01L51/56 ,  G09G3/20 ,  G06F3/041 ,  H01L27/12 ,  H01L29/66 ,  G09G3/3233 ,  H01L29/786

Abstract: A novel display panel that is highly convenient or reliable is provided. The display panel includes a display region, and the display region includes a first group of pixels, a second group of pixels, a third group of pixels, a fourth group of pixels, a first scan line, a second scan line, a first signal line, and a second signal line. The first group of pixels include a first pixel and are arranged in a row direction. The second group of pixels include a second pixel and are arranged in the row direction. The third group of pixels include a first pixel and are arranged in a column direction that intersects the row direction. The fourth group of pixels include a second pixel and are arranged in the column direction. The first signal line is electrically connected to the third group of pixels and the second signal line is electrically connected to the fourth group of pixels. The first scan line is electrically connected to the first group of pixels and the second scan line is electrically connected to the second group of pixels.

公开(公告)号：US10943547B2

公开(公告)日：2021-03-09

申请号：US15819236

申请日：2017-11-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Jun Koyama ,  Hiroyuki Miyake ,  Kouhei Toyotaka

IPC: G09G3/34 ,  G09G3/36 ,  G09G3/20

Abstract: A liquid crystal display device comprising a backlight and a pixel portion including first to 2n-th scan lines, wherein, in a first case of expressing a color image, first pixels controlled by the first to n-th scan lines are configured to express a first image using at least one of first to third hues supplied in a first rotating order, and second pixels controlled by the (n+1)-th to 2n-th scan lines are configured to express a second image using at least one of the first to third hues supplied in a second rotating order, wherein, in a second case of expressing a monochrome image, the first and second pixels controlled by the first to 2n-th scan lines are configured to express the monochrome image by external light reflected by the reflective pixel electrode, and wherein the first rotating order is different from the second rotating order.

公开(公告)号：US20200168739A1

公开(公告)日：2020-05-28

申请号：US16778336

申请日：2020-01-31

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Masashi Tsubuku ,  Kosei Noda ,  Kouhei Toyotaka ,  Kazunori Watanabe ,  Hikaru Harada

IPC: H01L29/786 ,  H01L29/423 ,  H01L29/417 ,  H01L27/12 ,  H01L29/24 ,  H01L27/108 ,  G06F15/76 ,  H01L49/02 ,  H01L27/11

Abstract: An object is to provide a memory device including a memory element that can be operated without problems by a thin film transistor with a low off-state current. Provided is a memory device in which a memory element including at least one thin film transistor that includes an oxide semiconductor layer is arranged as a matrix. The thin film transistor including an oxide semiconductor layer has a high field effect mobility and low off-state current, and thus can be operated favorably without problems. In addition, the power consumption can be reduced. Such a memory device is particularly effective in the case where the thin film transistor including an oxide semiconductor layer is provided in a pixel of a display device because the memory device and the pixel can be formed over one substrate.

公开(公告)号：US10573667B2

公开(公告)日：2020-02-25

申请号：US15366255

申请日：2016-12-01

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hisao Ikeda ,  Kouhei Toyotaka ,  Hideaki Shishido ,  Hiroyuki Miyake ,  Kohei Yokoyama ,  Yasuhiro Jinbo ,  Yoshitaka Dozen ,  Takaaki Nagata ,  Shinichi Hirasa

IPC: H01L27/12 ,  H01L27/32 ,  G09G3/20 ,  G09G3/3233 ,  G09G3/36 ,  G09G5/391

Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.