SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF

    公开(公告)号:US20230137800A1

    公开(公告)日:2023-05-04

    申请号:US18090918

    申请日:2022-12-29

    Abstract: A semiconductor package includes a semiconductor element, a wiring structure, an encapsulation structure, and a solder ball. The semiconductor element includes a plurality of pins. A side of the wiring structure is electrically connected to the plurality of pins of the semiconductor element. The wiring structure includes at least two first wiring layers. A first insulating layer is disposed between adjacent two first wiring layers of the at least two first wiring layers. The first insulating layer includes a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The encapsulation structure at least partially surrounds the semiconductor element. The solder ball is located on a side of the wiring structure away from the semiconductor element. The solder ball is electrically connected to the at least two first wiring layers.

    CHIP PACKAGE METHOD AND CHIP PACKAGE STRUCTURE

    公开(公告)号:US20220084973A1

    公开(公告)日:2022-03-17

    申请号:US17451621

    申请日:2021-10-20

    Abstract: Chip package structure is provided. The chip package structure includes: a chip, the chip including metal pins; an organic polymer material layer, the organic polymer material layer being located on a side of the metal pins away from the chip, the organic polymer material layer including a first via hole, and the organic polymer material layer including a first surface away from the chip; metal parts, at least a portion of the metal parts being located in the first via hole, the metal parts and metal pins being electrically connected, the metal parts including a second surface away from the chip, and the second surface and the first surface being flush to each other; and an encapsulating layer, the encapsulating layer being located on a side of the metal parts away from the organic polymer material layer.

    DRIVE CIRCUIT AND DRIVE METHOD THEREOF, AND PANEL AND DRIVE METHOD THEREOF

    公开(公告)号:US20220270555A1

    公开(公告)日:2022-08-25

    申请号:US17733534

    申请日:2022-04-29

    Abstract: A panel and its drive method are provided. The panel includes: a substrate, an array layer and an electrode array layer, where the array layer is on a side of the substrate; the electrode array layer is on a side of the array layer away from the substrate; and the array layer includes an active layer, a gate metal layer and a source/drain metal layer; the substrate includes a plurality of drive units arranged in an array, a plurality of scan line groups and a plurality of data line groups; the scan line group includes first scan lines and second scan lines adjacent to the first scan lines, extending in a first direction; and the data line group includes first data lines and second data lines adjacent to the first data lines, extending in a second direction.

    DISPLAY DEVICE AND VEHICLE
    15.
    发明申请

    公开(公告)号:US20210402879A1

    公开(公告)日:2021-12-30

    申请号:US17016776

    申请日:2020-09-10

    Inventor: Ming WANG Feng QIN

    Abstract: Provided are a display panel and a vehicle. The display device includes a knob and a main display panel; the knob includes a first magnetic adhering piece; the display device further includes a second magnetic adhering structure, and the second magnetic adhering structure is disposed on a non-light exiting side of the main display panel; the second magnetic adhering structure includes a plurality of first magnetic adhering regions, and at least two first magnetic adhering regions are not overlapped; when the knob is magnetically adhered to any one of the plurality of first magnetic adhering regions, the knob is disposed on a light exiting side of the main display panel.

    SEMICONDUCTOR PACKAGE AND FORMATION METHOD THEREOF

    公开(公告)号:US20210351042A1

    公开(公告)日:2021-11-11

    申请号:US16913020

    申请日:2020-06-26

    Abstract: A semiconductor package and a method of forming the semiconductor package are provided. The method includes providing a first substrate, forming a wiring structure containing at least two first wiring layers, disposing a first insulating layer between adjacent two first wiring layers, and patterning the first insulating layer to form a plurality of first through-holes. The adjacent two first wiring layers are electrically connected to each other through the plurality of first through-holes. The method also includes providing at least one semiconductor element each including a plurality of pins. In addition, the method includes disposing the plurality of pins of the each semiconductor element on a side of the wiring structure away from the first substrate. Further, the method includes encapsulating the at least one semiconductor element, and placing a ball on a side of the wiring structure away from the at least one semiconductor element.

    PACKAGING METHOD OF PANEL-LEVEL CHIP DEVICE

    公开(公告)号:US20210280525A1

    公开(公告)日:2021-09-09

    申请号:US17330236

    申请日:2021-05-25

    Abstract: Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

    PANEL-LEVEL CHIP DEVICE AND PACKAGING METHOD THEREOF

    公开(公告)号:US20200328159A1

    公开(公告)日:2020-10-15

    申请号:US16457290

    申请日:2019-06-28

    Abstract: A panel-level chip device and a packaging method for forming the panel-level chip device are provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

    DRIVE CIRCUIT AND DRIVE METHOD THEREOF, AND PANEL AND DRIVE METHOD THEREOF

    公开(公告)号:US20200316591A1

    公开(公告)日:2020-10-08

    申请号:US16457939

    申请日:2019-06-29

    Abstract: A drive circuit and its drive method, and a panel and its drive method are provided. The drive circuit includes a step-up unit, a plurality of signal input terminals and a signal output terminal. The step-up unit includes a first module, a second module and a first capacitor. The first module is configured to transmit a signal of a third signal input terminal to a first electrode of the first capacitor. The second module is configured to transmit a signal of a fourth signal input terminal to a second electrode of the first capacitor at a first time period which generates a voltage difference between two electrodes of the first capacitor, and to transmit the signal of the fourth signal input terminal to the second electrode of the first capacitor at a second time period which further increases a signal of the first electrode of the first capacitor.

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