公开(公告)号：US5465380A

公开(公告)日：1995-11-07

申请号：US222949

申请日：1994-04-04

申请人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

发明人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F9/00

CPC分类号： G06F9/54 ,  G06F15/161

摘要： A parallel processor system which includes a plurality of processors each for executing at least one of a plurality of mutually associated programs and a transfer circuit. The transfer circuit is connected to the processors, and is provided for transferring the data outputted from any one of the programs during execution of one program by any one of the processors to other processors to which a receiving program is allotted. The transfer operation is performed in response to a program identification code outputted during execution of the one program by one processor to identify the receiving program.

摘要翻译： 一种并行处理器系统，其包括多个处理器，每个处理器用于执行多个相互关联的程序和传送电路中的至少一个。 传送电路连接到处理器，并且被提供用于将由任何一个处理器执行一个程序期间的任何一个程序输出的数据传送到分配了接收程序的其他处理器。 响应于由一个处理器执行一个程序期间输出的节目识别码来执行传送操作以识别接收节目。

公开(公告)号：US4899273A

公开(公告)日：1990-02-06

申请号：US940539

申请日：1986-12-10

申请人： Koichiro Omoda ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshio Takamine ,  Shigeo Nagashima ,  Masayuki Miyoshi ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

发明人： Koichiro Omoda ,  Shunsuke Miyamoto ,  Takayuki Nakagawa ,  Yoshio Takamine ,  Shigeo Nagashima ,  Masayuki Miyoshi ,  Yoshiharu Kazama ,  Yoshiaki Kinoshita

IPC分类号： G06F17/16 ,  G01R31/317 ,  G01R31/3173 ,  G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5022 ,  G01R31/31705 ,  G01R31/3173

摘要： A computer implemented logic simulation method, for inspecting logical operations of large scale logic circuits, computes a variation of an output of at least one latch in a clock synchronized logic circuit. The clock-synchronized logic circuit contains a combination logic circuit and a plurality of logic gates. Each of the logic gates have at least one input signal and several other inputs connected to clocking signal sources of different phases. The latch is activated by the rise or fall of the clock signals for holding the output from the combination logic circuit. The method thus implements sampling instants of the output for ascertaining the logical operations of the large scale circuits.

摘要翻译： 一种用于检查大规模逻辑电路的逻辑运算的计算机实现的逻辑模拟方法，计算时钟同步逻辑电路中至少一个锁存器的输出的变化。 时钟同步逻辑电路包含组合逻辑电路和多个逻辑门。 每个逻辑门具有至少一个输入信号和几个其他输入，其连接到不同相位的时钟信号源。 锁存器由用于保持组合逻辑电路的输出的时钟信号的上升或下降而被激活。 因此，该方法实现了输出的采样时刻，以确定大规模电路的逻辑运算。

公开(公告)号：US5113390A

公开(公告)日：1992-05-12

申请号：US508065

申请日：1990-04-10

申请人： Takehisa Hayashi ,  Koichiro Omoda ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

发明人： Takehisa Hayashi ,  Koichiro Omoda ,  Teruo Tanaka ,  Naoki Hamanaka ,  Shigeo Nagashima

IPC分类号： H04L12/935 ,  H04L12/937

CPC分类号： H04L49/3018 ,  H04L49/254 ,  H04L49/3027

摘要： A computer system having a plurality of processors assigned first and second address portions are connected to a plurality of switch circuits. A first group transfer networks are connected to a corresponding first group of the plurality of switch circuits. Each of the transfer networks concurrently transfer data among the switch circuits. The switch circuits are provided to processors of a first kind arranged in a plurality of processor groups. The processor groups of the first kind include processors with different values for first address portions and the same value for second address portions. Additional transfer networks, processors and switches functioning in a similar manner are provided to expand the above system. In another embodiment of the present invention a data transfer network is provided having a plurality of processors for data transfer. The network includes a plurality of multistage switches each belonging to one of plural stages and connected to the switches of a preceding stage and to switches of the succeeding stage. Each of the switches are arranged to receive packets from a preceding switch. A packet includes a target process address and data to be transferred. A path select device is connected to receive packets and is also connected to plural switches belonging to a next stage for the transfer of the received partial addresses and partial data. A control device is connected to receive the partial addresses and partial data and is responsive to a predetermined bit within the received partial addresses. The control means is responsive to the arrival of the first partial address of the packet.

公开(公告)号：US4985827A

公开(公告)日：1991-01-15

申请号：US226376

申请日：1988-07-29

申请人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Junji Nakagoshi ,  Kazuo Ojima

发明人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Junji Nakagoshi ,  Kazuo Ojima

IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F15/80

CPC分类号： G06F15/8092 ,  G06F15/8084

摘要： A computer comprising a circuit for writing a group of ordered data elements onto the main storage; a circuit for reading said group of data from the main storage; and a circuit which is connected to the writing circuit and to the reading circuit, and which ensures the sequence of main storage references between said writing circuit and said reading circuit such that said reading circuit will not read the data elements that have not yet been written by said writing circuit among said group of data elements.

公开(公告)号：US4910667A

公开(公告)日：1990-03-20

申请号：US184788

申请日：1988-04-22

申请人： Teruo Tanaka ,  Koichiro Omoda ,  Yasuhiro Inagami ,  Takayuki Nakagawa ,  Mamoru Sugie ,  Shigeo Nagashima

发明人： Teruo Tanaka ,  Koichiro Omoda ,  Yasuhiro Inagami ,  Takayuki Nakagawa ,  Mamoru Sugie ,  Shigeo Nagashima

IPC分类号： G06F12/08 ,  G06F15/78 ,  G06F17/16

CPC分类号： G06F15/8053

摘要： In a vector processor having vector registers, a vector buffer storage for temporarily storing vector data is arranged closer to the vector registers than to a main storage, and a vector buffer storage control including an identification storage for storing identification information of the vector data stored at storage locations of the buffer storage and a check circuit for checking if the vector data identification information is in the identificatgion storage is provided. The vector buffer storage control checks if the identification information of the vector data designated by a vector data fetch instruction for the main storage is in the indentification storage, and if it is in the identification storage, it fetches the vector data from the buffer storage and transfers it to the vector register, and if it is not in the identification storage, it instructs to fetch the vector data from the main storage, transfers the vector data fetched from the main storage to the vector register and stores it into the buffer storage.

摘要翻译： 在具有向量寄存器的向量处理器中，用于临时存储向量数据的向量缓冲存储器比向主存储器靠近向量寄存器布置，并且向量缓冲器存储控制包括用于存储存储在 提供缓冲存储器的存储位置和用于检查矢量数据识别信息是否在识别存储器中的检查电路。 向量缓冲存储控制检查由主存储器的矢量数据获取指令指定的矢量数据的识别信息是否在识别存储器中，并且如果它在识别存储器中，则从缓冲存储器中取出向量数据， 将其传送到向量寄存器，如果不在识别存储器中，则指示从主存储器获取向量数据，将从主存储器获取的向量数据传送到向量寄存器，并将其存储到缓冲存储器中。

公开(公告)号：US4782441A

公开(公告)日：1988-11-01

申请号：US872396

申请日：1986-06-10

申请人： Yasuhiro Inagami ,  Shigeo Nagashima ,  Koichiro Omoda ,  Takayuki Nakagawa ,  Teruo Tanaka

发明人： Yasuhiro Inagami ,  Shigeo Nagashima ,  Koichiro Omoda ,  Takayuki Nakagawa ,  Teruo Tanaka

IPC分类号： G06F9/46 ,  G06F9/38 ,  G06F9/48 ,  G06F15/78 ,  G06F17/16 ,  G06F9/28 ,  G06F7/00

CPC分类号： G06F15/8053

摘要： In a processor such as a vector processor in which a plurality of data are processed by one instruction and a plurality of instructions are parallely processed, apparatus is provided for storing, during an interruption of the program currently being executed, the instructions being executed in the conceptual order of appearance in the program of the instruction being executed, and the sequential count of the sets of data processed. The stored information is used to restart the execution of the interrupted program at the appropriate point.

摘要翻译： 在其中通过一个指令处理多个数据并且多个指令并行处理的诸如矢量处理器的处理器中，提供装置，用于在当前执行的程序的中断期间存储在 正在执行的指令的程序中出现的概念顺序，以及处理的数据组的顺序计数。 存储的信息用于在适当的点重新启动中断的程序的执行。

公开(公告)号：US4680730A

公开(公告)日：1987-07-14

申请号：US629042

申请日：1984-07-09

申请人： Koichiro Omoda ,  Shigeo Nagashima

发明人： Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F17/16 ,  G06F15/78 ,  G06F12/06

CPC分类号： G06F15/8084

摘要： In a storage control apparatus only vector elements indicated as write data by a corresponding mask information among the vector elements stored in a storage device are stored to the pertinent memory locations of a desired vector register in the vector processor based on the mask information which indicates whether or not the write operation is required (for example, "1" indicates that the write operation is necessary and "0" indicates that the write operation is unnecessary). When the mask information indicates that the write operation is not required, the storage control apparatus controls operations to prevent the memory bank of the main storage from being set to the busy state, thereby eliminating the memory bank conflict which should not take place in accordance with the intrinsic system characteristics.

摘要翻译： 在存储控制装置中，根据存储在存储装置中的向量元素中的对应的掩模信息指示为写入数据的向量元素，根据掩码信息，存储在向量处理器中的期望向量寄存器的相关存储单元中， 或者不需要写入操作（例如，“1”表示写入操作是必需的，“0”表示不需要写入操作）。 当掩模信息指示不需要写入操作时，存储控制装置控制操作以防止主存储器的存储体被设置为忙状态，从而消除了不应该根据 内在系统特征。

公开(公告)号：US5301322A

公开(公告)日：1994-04-05

申请号：US912215

申请日：1992-07-10

申请人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

发明人： Naoki Hamanaka ,  Teruo Tanaka ,  Koichiro Omoda ,  Shigeo Nagashima

IPC分类号： G06F9/46 ,  G06F15/16 ,  G06F9/00

CPC分类号： G06F9/54 ,  G06F15/161

摘要： A parallel processor system includes a transfer circuit and a plurality of processors each of which executes at least one of a plurality of mutually associated programs. The transfer circuit transfers data from a sending program allotted to one processor to a receiving program allotted to another processor by identifying the other processor and the receiving program based on a job number and within-job process number outputted by the sending program.

摘要翻译： 并行处理器系统包括传送电路和多个处理器，每个处理器执行多个相互关联的程序中的至少一个。 传送电路根据发送程序输出的作业号和作业内编号，通过识别其他处理器和接收程序，将数据从分配给一个处理器的发送程序传送到分配给另一个处理器的接收程序。

公开(公告)号：US5010477A

公开(公告)日：1991-04-23

申请号：US109293

申请日：1987-10-15

申请人： Koichiro Omoda ,  Teruo Tanaka ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Shigeo Nagashima

发明人： Koichiro Omoda ,  Teruo Tanaka ,  Junji Nakagoshi ,  Naoki Hamanaka ,  Shigeo Nagashima

IPC分类号： G06F15/80

CPC分类号： G06F15/8092 ,  G06F15/8015

摘要： A parallel processor system having a plurality of processor elements includes transfer information generation circuit for generating transfer information by adding to vector data a data identifier for the vector data and a destination processor element number, transmission circuit for sending the transfer information to a data communication path, receive circuit for holding the transfer information sent from the data communication path, and vector register for continuously reading related element data from the receive circuit based on the data identifiers generated by the transfer information generation circuit.

摘要翻译： 具有多个处理器单元的并行处理器系统包括：传送信息生成电路，用于通过向矢量数据添加用于矢量数据的数据标识符和目的处理器单元号来生成传送信息，发送电路，用于将传送信息发送到数据通信路径 ，用于保持从数据通信路径发送的传送信息的接收电路，以及用于基于由传送信息生成电路产生的数据标识符从接收电路连续读取相关元素数据的向量寄存器。

公开(公告)号：US5867679A

公开(公告)日：1999-02-02

申请号：US647773

申请日：1991-01-30

申请人： Teruo Tanaka ,  Naoki Hamanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Junji Nakagoshi ,  Kazuo Ojima

发明人： Teruo Tanaka ,  Naoki Hamanaka ,  Koichiro Omoda ,  Shigeo Nagashima ,  Akira Muramatsu ,  Ikuo Yoshihara ,  Kazuo Nakao ,  Junji Nakagoshi ,  Kazuo Ojima

IPC分类号： G06F9/44 ,  G06F15/17 ,  G06F15/80 ,  G06F15/82

CPC分类号： G06F15/8015 ,  G06F9/4494 ,  G06F15/17

摘要： A parallel computer system includes a plurality of processors, each of which is placed in data communication with an interconnecting network. Pairs of a data signal and a data identification code, predetermined for the data signal, are received by each processor and stored in a memory. Structure is provided for reading a data signal belonging to one of the pairs having a data identification code designated by a data readout instruction.

摘要翻译： 并行计算机系统包括多个处理器，每个处理器与互连网络进行数据通信。 数据信号对和数据信号预定的数据识别码由每个处理器接收并存储在存储器中。 提供结构用于读取属于其中一对的数据信号，该数据信号具有由数据读出指令指定的数据识别码。