公开(公告)号：US08953404B2

公开(公告)日：2015-02-10

申请号：US13185127

申请日：2011-07-18

申请人： Yasuo Kanda ,  Koichi Amari ,  Shunsaku Tokito ,  Yuji Torige ,  Takayuki Arima ,  Takafumi Kunihiro

发明人： Yasuo Kanda ,  Koichi Amari ,  Shunsaku Tokito ,  Yuji Torige ,  Takayuki Arima ,  Takafumi Kunihiro

IPC分类号： G11C17/18 ,  G11C17/00 ,  H01L23/525 ,  G11C17/16

CPC分类号： H01L23/5256 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

摘要翻译： 一种半导体器件具有电熔丝元件，包括：第一细丝; 连接到第一细丝的第二细丝; 以及串联读出部，连接到与第一细丝连接的第一丝的另一端相反的第一丝的端部，串联读出部读取第一细丝和第二细丝的串联电阻。

公开(公告)号：US07684231B2

公开(公告)日：2010-03-23

申请号：US11609631

申请日：2006-12-12

申请人： Atsushi Hayashi ,  Shunsaku Tokito ,  Hiroshi Yoshihara ,  Yuuki Fujiyama

发明人： Atsushi Hayashi ,  Shunsaku Tokito ,  Hiroshi Yoshihara ,  Yuuki Fujiyama

IPC分类号： G11C11/00

CPC分类号： G11C7/22 ,  G11C2207/2227

摘要： Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

摘要翻译： 方法和装置提供用于控制SRAM存储器，SRAM存储器包括以行（字线）和列（位线）排列的多个存储单元，包括：将用于输入的数据的状态反转到一个或多个列 的阵列; 以及将所述反转的数据存储在所述一个或多个列的一个或多个存储单元中。

公开(公告)号：US07596040B2

公开(公告)日：2009-09-29

申请号：US11778173

申请日：2007-07-16

申请人： Shunsaku Tokito

发明人： Shunsaku Tokito

IPC分类号： G11C7/00

CPC分类号： G11C11/419

摘要： Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit.

摘要翻译： 方法和装置提供通过真实位线（BLT）和互补位线（BLC）将数据写入SRAM存储单元的反并行存储电路并从其读取数据; 并且在将逻辑低电平写入反并行存储电路的操作期间防止互补位线（BLC）从预充电逻辑高电压电平显着下降。

公开(公告)号：US20080137451A1

公开(公告)日：2008-06-12

申请号：US11609631

申请日：2006-12-12

申请人： Atsushi Hayashi ,  Shunsaku Tokito ,  Hiroshi Yoshihara ,  Yuuki Fujiyama

发明人： Atsushi Hayashi ,  Shunsaku Tokito ,  Hiroshi Yoshihara ,  Yuuki Fujiyama

IPC分类号： G11C7/10

CPC分类号： G11C7/22 ,  G11C2207/2227

摘要： Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), comprising: inverting a state of data for input to one or more columns of the array; and storing the inverted data in one or more memory cells of the one or more columns.

摘要翻译： 方法和装置提供用于控制SRAM存储器，SRAM存储器包括以行（字线）和列（位线）排列的多个存储单元，包括：将用于输入的数据的状态反转到一个或多个列 的阵列; 以及将所述反转的数据存储在所述一个或多个列的一个或多个存储单元中。

公开(公告)号：US07376028B2

公开(公告)日：2008-05-20

申请号：US10561965

申请日：2004-07-05

申请人： Shunsaku Tokito

发明人： Shunsaku Tokito

IPC分类号： G11C7/00

CPC分类号： G11C11/419

摘要： A semiconductor memory device having a dummy memory cell and a reading method of the same, wherein provision is made of a memory cell 11 connected to a word line WL and a pair of bit lines BL and xBL, a dummy memory cell 12 connected to a word line WL and a pair of dummy bit lines DBL and xDBL, and a word line driver 13 for activating the word line at a common timing, and when the data is read out from the memory cell, a timing of the reading of the data is determined in accordance with a level of the dummy bit lines connected to the dummy memory, and when a voltage difference of a pair of dummy bit lines becomes a threshold voltage, the word line driver deactivates the word line and precharges the dummy bit lines.

摘要翻译： 具有虚拟存储单元及其读取方法的半导体存储器件，其中提供连接到字线WL和一对位线BL和xBL的存储单元11，与 字线WL和一对虚拟位线DBL和xDBL，以及用于在公共定时激活字线的字线驱动器13，并且当从存储器单元读出数据时，读取数据的定时 根据连接到虚拟存储器的虚拟位线的电平来确定，并且当一对虚拟位线的电压差成为阈值电压时，字线驱动器停用字线并对虚拟位线进行预充电。

公开(公告)号：US20080052504A1

公开(公告)日：2008-02-28

申请号：US11509493

申请日：2006-08-24

申请人： Atsushi Tsuji ,  Chiaki Takano ,  Atsuo Mangyo ,  Masaaki Nozaki ,  Shunsaku Tokito ,  Hiroaki Terakawa

发明人： Atsushi Tsuji ,  Chiaki Takano ,  Atsuo Mangyo ,  Masaaki Nozaki ,  Shunsaku Tokito ,  Hiroaki Terakawa

IPC分类号： G06F15/177

CPC分类号： G06F9/4418

摘要： Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device. Alternatively, the configuration data may be accessed and retrieved from a local storage medium individually located in each processor, thereby re-booting only those inactive processors and without re-initializing the entire system.

摘要翻译： 以多处理器配置布置的用于基本并行操作的处理器接收它们的初始化数据，以便开始诸如图形计算，实时多媒体流等操作。由于处理负载的变化，一个或多个处理器可能是 停用 随后，负载增加到要求全部或一些停用处理器再次活动的水平。 在这种情况下，整个系统的启动过程不会执行，因为这将是耗时且浪费的; 相反，响应于控制信号，仅通过选择由另一个处理器，控制器或任何其他智能可编程设备提供的配置数据来重新初始化先前处于非活动模式的处理器。 或者，可以从单独位于每个处理器中的本地存储介质访问和检索配置数据，从而仅重新引导那些不活动的处理器，并且不重新初始化整个系统。