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    SEMICONDUCTOR DEVICE
    2.
    发明申请
    SEMICONDUCTOR DEVICE 失效
    半导体器件

    公开(公告)号：US20120039105A1

    公开(公告)日：2012-02-16

    申请号：US13138907

    申请日：2010-06-08

    申请人： Yuji Torige

    发明人： Yuji Torige

    IPC分类号： G11C17/16

    CPC分类号： G11C17/16 ,  G11C13/0004 ,  G11C13/003 ,  G11C17/18 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11286

    摘要： Both decreasing access time and power consumption and improving storage bit count per one word line are compatibly attained. A memory cell array 1 has a configuration in which at least one row of memory cells MC having a fuse device F with a resistance value variable according to a flowing current and a plurality of cell transistors (TRB1 and TRB2) connected in parallel with respect to the fuse device F is arranged. In the relevant semiconductor device, out of the plurality of cell transistors (TRB1 and TRB2), the number of cell transistors turned ON is controllable by a writing control signal (WRITE) inputted from outside and an internal logic circuit 5 (and a word line drive circuit 4).

    摘要翻译： 同时实现了每一个字线的访问时间和功耗的降低以及提高存储位计数。 存储单元阵列1具有这样的结构，其中具有根据流动电流具有可变电阻值的熔丝器件F的至少一行存储单元MC和多个单元晶体管（TRB1和TRB2）相对于 保险丝装置F被布置。 在相关半导体器件中，在多个单元晶体管（TRB1和TRB2）中，由外部输入的写控制信号（WRITE）和内部逻辑电路5（以及字线 驱动电路4）。

    Semiconductor device
    3.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08456884B2

    公开(公告)日：2013-06-04

    申请号：US13138907

    申请日：2010-06-08

    申请人： Yuji Torige

    发明人： Yuji Torige

    IPC分类号： G11C17/00

    CPC分类号： G11C17/16 ,  G11C13/0004 ,  G11C13/003 ,  G11C17/18 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11286

    摘要： Both decreasing access time and power consumption and improving storage bit count per one word line are compatibly attained. A memory cell array 1 has a configuration in which at least one row of memory cells MC having a fuse device F with a resistance value variable according to a flowing current and a plurality of cell transistors (TRB1 and TRB2) connected in parallel with respect to the fuse device F is arranged. In the relevant semiconductor device, out of the plurality of cell transistors (TRB1 and TRB2), the number of cell transistors turned ON is controllable by a writing control signal (WRITE) inputted from outside and an internal logic circuit 5 (and a word line drive circuit 4).

    摘要翻译： 同时实现了每一个字线的访问时间和功耗的降低以及提高存储位计数。 存储单元阵列1具有这样的结构，其中具有根据流动电流具有可变电阻值的熔丝器件F的至少一行存储单元MC和多个单元晶体管（TRB1和TRB2）相对于 保险丝装置F被布置。 在相关半导体器件中，在多个单元晶体管（TRB1和TRB2）中，由外部输入的写控制信号（WRITE）和内部逻辑电路5（以及字线 驱动电路4）。