公开(公告)号：US20070047349A1

公开(公告)日：2007-03-01

申请号：US11218009

申请日：2005-09-01

申请人： Shunsaku Tokito

发明人： Shunsaku Tokito

IPC分类号： G11C7/00

CPC分类号： G11C11/413 ,  G11C7/12

摘要： Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell.

公开(公告)号：US07676683B2

公开(公告)日：2010-03-09

申请号：US11509493

申请日：2006-08-24

申请人： Atsushi Tsuji ,  Chiaki Takano ,  Atsuo Mangyo ,  Masaaki Nozaki ,  Shunsaku Tokito ,  Hiroaki Terakawa

发明人： Atsushi Tsuji ,  Chiaki Takano ,  Atsuo Mangyo ,  Masaaki Nozaki ,  Shunsaku Tokito ,  Hiroaki Terakawa

IPC分类号： G06F1/00 ,  G06F9/00 ,  G06F13/00 ,  G06F12/00

CPC分类号： G06F9/4418

摘要： Processors arranged in a multi-processor configuration for substantially parallel operations receive their initialization data in order to start operations, such as graphics computations, real-time multimedia streaming, etc. Due to a change in the processing load, one or more processors might be deactivated. Subsequently, the load increases to such a level that requires all or some of the deactivated processors to be active again. In this case, the boot-up process of the entire system is not carried out as it would be time-consuming and wasteful; instead, responsive to a control signal only those processors that were previously in inactive mode are re-initialized by selecting a configuration data supplied by another processor, controller or any other intelligent programmable device. Alternatively, the configuration data may be accessed and retrieved from a local storage medium individually located in each processor, thereby re-booting only those inactive processors and without re-initializing the entire system.

摘要翻译： 以多处理器配置布置的用于基本并行操作的处理器接收它们的初始化数据，以便开始诸如图形计算，实时多媒体流等操作。由于处理负载的变化，一个或多个处理器可能是 停用 随后，负载增加到要求全部或一些停用处理器再次活动的水平。 在这种情况下，整个系统的启动过程不会执行，因为这将是耗时且浪费的; 相反，响应于控制信号，仅通过选择由另一个处理器，控制器或任何其他智能可编程设备提供的配置数据来重新初始化先前处于非活动模式的处理器。 或者，可以从单独位于每个处理器中的本地存储介质访问和检索配置数据，从而仅重新引导那些不活动的处理器，并且不重新初始化整个系统。

公开(公告)号：US07545670B2

公开(公告)日：2009-06-09

申请号：US11775546

申请日：2007-07-10

申请人： Shunsaku Tokito ,  Atsushi Hayashi

发明人： Shunsaku Tokito ,  Atsushi Hayashi

IPC分类号： G11C11/40

CPC分类号： G11C8/14 ,  G11C11/418

摘要： Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit.

摘要翻译： 方法和装置提供通过真实位线（BLT）和互补位线（BLC）将数据写入SRAM存储单元的反并行存储电路并从其读取数据; 并且在从反并行存储电路读取逻辑1的操作期间防止互补位线（BLC）从预充电电平显着下降。

公开(公告)号：US20090021997A1

公开(公告)日：2009-01-22

申请号：US11778173

申请日：2007-07-16

申请人： Shunsaku Tokito

发明人： Shunsaku Tokito

IPC分类号： G11C7/00

CPC分类号： G11C11/419

摘要： Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge, logic high voltage level during operations in which a logic low level is written into the anti-parallel storage circuit.

摘要翻译： 方法和装置提供通过真实位线（BLT）和互补位线（BLC）将数据写入SRAM存储单元的反并行存储电路并从其读取数据; 并且在将逻辑低电平写入反并行存储电路的操作期间防止互补位线（BLC）从预充电逻辑高电压电平显着下降。

公开(公告)号：US20080112234A1

公开(公告)日：2008-05-15

申请号：US11559982

申请日：2006-11-15

申请人： Shunsaku Tokito

发明人： Shunsaku Tokito

IPC分类号： G11C7/00

CPC分类号： G11C7/12 ,  G11C11/413

摘要： Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.

摘要翻译： 方法和装置提供用于控制SRAM存储器，SRAM存储器包括排列成行（字线）和列（位线）阵列的多个存储单元，包括：将至少一个位线的逻辑值映射到 全局位线 响应于在连续的读取和写入操作期间至少一次循环到存储器单元的时钟信号，将全局位线驱动为预充电逻辑值; 在将逻辑值写入与预充电逻辑值相反的位线的写入操作期间，将全局位线保持在预充电逻辑值。

公开(公告)号：US20120026822A1

公开(公告)日：2012-02-02

申请号：US13185127

申请日：2011-07-18

申请人： Yasuo Kanda ,  Koichi Amari ,  Shunsaku Tokito ,  Yuji Torige ,  Takayuki Arima ,  Takafumi Kunihiro

发明人： Yasuo Kanda ,  Koichi Amari ,  Shunsaku Tokito ,  Yuji Torige ,  Takayuki Arima ,  Takafumi Kunihiro

IPC分类号： G11C17/16

CPC分类号： H01L23/5256 ,  G11C17/16 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has an electrical fuse element including: a first filament; a second filament connected to the first filament; and a series readout section connected to an end of the first filament opposite to another end of the first filament connected to the second filament, the series readout section reading series resistance of the first filament and the second filament.

摘要翻译： 一种半导体器件具有电熔丝元件，包括：第一细丝; 连接到第一细丝的第二细丝; 以及串联读出部，连接到与第一细丝连接的第一丝的另一端相反的第一丝的端部，串联读出部读取第一细丝和第二细丝的串联电阻。

公开(公告)号：US20090016122A1

公开(公告)日：2009-01-15

申请号：US11775546

申请日：2007-07-10

申请人： Shunsaku Tokito ,  Atsushi Hayashi

发明人： Shunsaku Tokito ,  Atsushi Hayashi

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C8/14 ,  G11C11/418

摘要： Methods and apparatus provide for writing data into and reading data from an anti-parallel storage circuit of an SRAM memory cell via a true bit line (BLT) and a complementary bit line (BLC); and preventing the complementary bit line (BLC) from substantially dropping from a pre-charge level during operations in which a logic one is read from the anti-parallel storage circuit.

摘要翻译： 方法和装置提供通过真实位线（BLT）和互补位线（BLC）将数据写入SRAM存储单元的反并行存储电路并从其读取数据; 并且在从反并行存储电路读取逻辑1的操作期间防止互补位线（BLC）从预充电电平显着下降。

公开(公告)号：US07423900B2

公开(公告)日：2008-09-09

申请号：US11559982

申请日：2006-11-15

申请人： Shunsaku Tokito

发明人： Shunsaku Tokito

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C11/413

摘要： Methods and apparatus provide for controlling an SRAM memory, the SRAM memory including a plurality of memory cells arranged in an array of rows (word lines) and columns (bit lines), including: mirroring logic values of at least one of the bit lines to a global bit line; driving the global bit line to a pre-charge logic value in response to a clock signal that cycles at least one time during successive read and write operations to the memory cell; maintaining the global bit line at the pre-charge logic value during a write operation in which a logic value is written to the bit line that is opposite to the pre-charge logic value.

摘要翻译： 方法和装置提供用于控制SRAM存储器，SRAM存储器包括排列成行（字线）和列（位线）阵列的多个存储单元，包括：将至少一个位线的逻辑值映射到 全局位线 响应于在连续的读取和写入操作期间至少一次循环到存储器单元的时钟信号，将全局位线驱动为预充电逻辑值; 在将逻辑值写入与预充电逻辑值相反的位线的写入操作期间，将全局位线保持在预充电逻辑值。

公开(公告)号：US07242609B2

公开(公告)日：2007-07-10

申请号：US11218009

申请日：2005-09-01

申请人： Shunsaku Tokito

发明人： Shunsaku Tokito

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C11/413 ,  G11C7/12

摘要： Methods and apparatus provide for pre-charging a bit line and a complementary bit line of an SRAM memory cell of the SRAM memory to a voltage level below a power supply level, Vdd, of the SRAM memory prior to writing data to the memory cell.

摘要翻译： 方法和装置提供了在向存储器单元写入数据之前，将SRAM存储器的SRAM存储单元的位线和互补位线预充电至低于SRAM存储器的电源电平Vdd的电压电平。

公开(公告)号：US20070109895A1

公开(公告)日：2007-05-17

申请号：US10561965

申请日：2004-07-05

申请人： Shunsaku Tokito

发明人： Shunsaku Tokito

IPC分类号： G11C7/02

CPC分类号： G11C11/419

摘要： A semiconductor memory device having a dummy memory cell and a reading method of the same, wherein provision is made of a memory cell 11 connected to a word line WL and a pair of bit lines BL and xBL, a dummy memory cell 12 connected to a word line WL and a pair of dummy bit lines DBL and xDBL, and a word line driver 13 for activating the word line at a common timing, and when the data is read out from the memory cell, a timing of the reading of the data is determined in accordance with a level of the dummy bit lines connected to the dummy memory, and when a voltage difference of a pair of dummy bit lines becomes a threshold voltage, the word line driver deactivates the word line and precharges the dummy bit lines.

摘要翻译： 具有虚拟存储单元及其读取方法的半导体存储器件，其中提供连接到字线WL和一对位线BL和xBL的存储单元11，与 字线WL和一对虚拟位线DBL和xDBL，以及用于在公共定时激活字线的字线驱动器13，并且当从存储器单元读出数据时，读取数据的定时 根据连接到虚拟存储器的虚拟位线的电平来确定，并且当一对虚拟位线的电压差成为阈值电压时，字线驱动器停用字线并对虚拟位线进行预充电。