公开(公告)号：US06529435B2

公开(公告)日：2003-03-04

申请号：US10000313

申请日：2001-12-04

申请人： Yoshimasa Yagishita ,  Toshiya Uchida

发明人： Yoshimasa Yagishita ,  Toshiya Uchida

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C7/1006 ,  G11C11/4096 ,  G11C2211/4062

摘要： A semiconductor memory device which permits access even during refresh operation and also is low in power consumption. An address input circuit receives an input address, and a readout circuit reads out data from at least part of a subblock group arranged in a column or row direction and specified by the address input via the address input circuit. A refresh circuit refreshes at least part of a subblock group arranged in a row or column direction and intersecting with the subblock group from which data is read out by the readout circuit. A data restoration circuit restores data of a subblock where refresh operation and readout operation take place concurrently, with reference to data from the other subblocks and a parity block.

公开(公告)号：US6137348A

公开(公告)日：2000-10-24

申请号：US204171

申请日：1998-12-03

申请人： Toshiya Uchida ,  Yoshimasa Yagishita

发明人： Toshiya Uchida ,  Yoshimasa Yagishita

IPC分类号： G11C11/413 ,  G05F1/46 ,  G11C5/14 ,  G11C11/401 ,  G11C11/407 ,  G11C29/06 ,  G05F1/10

CPC分类号： G05F1/465

摘要： A novel semiconductor device having two different power circuits is disclosed. Even if the output of the stage before a voltage conversion circuit declines due to the decline of the level of the power circuits or the voltage drop through a resistor, the voltage conversion circuit performs a normal operation. The semiconductor device comprises a first power circuit for generating a first source voltage, a second power circuit for generating a second source voltage higher than the first source voltage, and a second power level detection circuit for detecting the second source voltage. The first power circuit changes the first source voltage in accordance with the result of detection by the second power level detection circuit.

摘要翻译： 公开了一种具有两个不同功率电路的新型半导体器件。 即使由于电源电路的电平下降或通过电阻器的电压降而在电压转换电路之前的级的输出下降，所以电压转换电路执行正常操作。 半导体器件包括用于产生第一源电压的第一电源电路，用于产生高于第一源电压的第二源电压的第二电源电路，以及用于检测第二源电压的第二功率电平检测电路。 第一电源电路根据第二功率电平检测电路的检测结果改变第一电源电压。

公开(公告)号：US06353572B2

公开(公告)日：2002-03-05

申请号：US09736124

申请日：2000-12-15

申请人： Yoshimasa Yagishita

发明人： Yoshimasa Yagishita

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C8/06 ,  G11C11/4082

摘要： The supply connecting circuit selects one input signal from a plurality of input signals corresponding to a plurality of select signals in response to the activation of any one of the select signals. The supply connecting circuit connects a supply to either of the inverting circuits in the latch depending on the input signal selected. The latch is forced to be unbalanced due to the activation of one inverting circuit so as to latch a value corresponding to the input signal selected by the select signal. A value to be latched is determined with the states of the input signals supplied at the activation of a select signal. This minimizes the settling periods of the input signals with respect to the select signals. As a result, the timing margins of the circuit increase, thereby realizing high speed operations.

摘要翻译： 电源连接电路响应于任一个选择信号的激活，从对应于多个选择信号的多个输入信号中选择一个输入信号。 供电连接电路根据所选择的输入信号将电源连接到锁存器中的任一个反相电路。 由于一个反相电路的激活，锁存器被迫不平衡，以便锁存与由选择信号选择的输入信号对应的值。 要锁存的值通过在激活选择信号时提供的输入信号的状态来确定。 这使得输入信号相对于选择信号的稳定周期最小化。 结果，电路的定时裕度增加，从而实现高速操作。

公开(公告)号：US08050121B2

公开(公告)日：2011-11-01

申请号：US12851452

申请日：2010-08-05

申请人： Yoshimasa Yagishita

发明人： Yoshimasa Yagishita

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C29/24 ,  G11C11/401 ,  G11C29/40 ,  G11C29/808 ,  G11C2029/5602 ,  Y10T29/49004

摘要： A plurality of memory blocks includes real memory cells and redundancy memory cells, are accessed independently during a normal operation mode, and are accessed simultaneously during a test mode in order for common data to be written to the plurality of memory blocks. A block control unit selects the plurality of memory blocks irrespective of a block address signal in order to execute a compression test. During the test mode, a redundancy access unit simultaneously accesses the redundancy memory cells of the plurality of memory blocks when a forced redundancy signal supplied to a block address terminal indicates first level. Therefore, the redundancy memory cells of the plurality of memory blocks may simultaneously access and test without providing any special terminal. As a result, before a defect is relieved, an operation test of the redundancy memory cells may efficiently execute, which may shorten the test time.

摘要翻译： 多个存储块包括实际存储单元和冗余存储单元，在正常操作模式期间被独立地访问，并且在测试模式期间被同时访问，以便将公共数据写入多个存储块。 块控制单元与块地址信号无关地选择多个存储块，以执行压缩测试。 在测试模式期间，当提供给块地址终端的强制冗余信号指示第一级时，冗余访问单元同时访问多个存储块的冗余存储单元。 因此，多个存储器块的冗余存储单元可以在不提供任何特殊终端的情况下同时访问和测试。 结果，在解除缺陷之前，可以有效地执行冗余存储单元的操作测试，这可能缩短测试时间。

公开(公告)号：US06552957B2

公开(公告)日：2003-04-22

申请号：US10050952

申请日：2002-01-22

申请人： Yoshimasa Yagishita

发明人： Yoshimasa Yagishita

IPC分类号： G11C800

CPC分类号： G11C7/109 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/22 ,  G11C8/06 ,  G11C8/18 ,  G11C11/4076 ,  G11C11/4093 ,  G11C2207/2227

摘要： A timing signal generator receives a plurality of control signals in synchronization with a clock signal, and generates a timing signal according to a combination of the control signals. A delay circuit delays an input signal received asynchronously to the clock signal by a predetermined time. A receiving circuit receives the input signal which is delayed by the delay circuit, in synchronization not with the clock signal but with the timing signal. Namely, the receiving circuit operates asynchronously to the clock signal, and receives only necessary input signals for the semiconductor integrated circuit. This lowers operation frequency of the receiving circuit, thereby reducing power consumption. The number of the circuits to be operated in synchronization with the clock signal can be reduced, by which reduces standby current. An increase in the standby current is gradual even when frequency of the clock signal goes high.

摘要翻译： 定时信号发生器与时钟信号同步地接收多个控制信号，并根据控制信号的组合产生定时信号。 延迟电路将与时钟信号异步接收的输入信号延迟预定时间。 接收电路接收由延迟电路延迟的输入信号，与时钟信号同步而不是与定时信号同步。 也就是说，接收电路与时钟信号异步工作，并且仅接收用于半导体集成电路的必要的输入信号。 这降低了接收电路的工作频率，从而降低了功耗。 可以减少与时钟信号同步操作的电路的数量，从而减少待机电流。 即使时钟信号的频率变高，待机电流的增加也是逐渐增加的。

公开(公告)号：US06532179B2

公开(公告)日：2003-03-11

申请号：US09814771

申请日：2001-03-23

申请人： Yoshimasa Yagishita

发明人： Yoshimasa Yagishita

IPC分类号： G11C700

CPC分类号： G11C11/4082 ,  G11C5/063 ,  G11C11/4087

摘要： The semiconductor integrated circuit according to the present invention comprises a plurality of receiving circuits each for receiving a plurality of input signals in synchronization with a timing signal. The input signals supplied to each of the receiving circuits are made equal in propagation delay times from their respective input terminals to the receiving circuit. Since the receiving circuits can receive the input signals of little skew, the timing margin required for the reception is minimized. That is, high speed operation becomes possible. At the same time, because the input signals corresponding to each individual receiving circuit are made equal in propagation delay time, the wiring for transmitting the input signals can be arranged in a minimum area. This can reduce the chip area, with reduction in chip costs.

摘要翻译： 根据本发明的半导体集成电路包括多个接收电路，每个接收电路用于与定时信号同步地接收多个输入信号。 提供给每个接收电路的输入信号在从它们各自的输入端到接收电路的传播延迟时间相等。 由于接收电路可以接收到少量偏移的输入信号，所以接收所需的定时裕度被最小化。 也就是说，高速操作成为可能。 同时，由于在各传播延迟时间使与各个接收电路相对应的输入信号相等，所以用于发送输入信号的布线可以布置在最小的区域中。 这可以减少芯片面积，降低芯片成本。

公开(公告)号：US06377509B2

公开(公告)日：2002-04-23

申请号：US09739972

申请日：2000-12-20

申请人： Yoshimasa Yagishita

发明人： Yoshimasa Yagishita

IPC分类号： G11C700

CPC分类号： G11C7/109 ,  G11C7/1006 ,  G11C7/1072 ,  G11C7/1078 ,  G11C8/20

摘要： The command decoder decodes a command signal to generate a command control signal. The mask circuit receives the command control signal to recognize the operating state of the memory core thereafter, and activates a mask signal when the command signal to be supplied anew is unacceptable. The control circuit disables an operation of the memory core corresponding to the command control signal when the mask signal is activated. Illegal commands are decided by the mask circuit alone. On this account, the control circuit need not be provided with a circuit for individually determining commands as illegal in accordance with actual operating states. Therefore, using the mask circuit makes it possible to prevent malfunctions resulting from illegal commands with facility and reliability. The intrinsic functions of the control circuit have only to be verified at the time of design and circuit modifications, which results in improving design efficiency.

摘要翻译： 命令解码器解码命令信号以产生命令控制信号。 掩模电路接收命令控制信号，以此后识别存储器芯的工作状态，并且当重新提供的命令信号不可接受时激活掩码信号。 当屏蔽信号被激活时，控制电路禁止对应于命令控制信号的存储器芯的操作。 非法命令由掩模电路单独决定。 因此，控制电路不需要设置用于根据实际操作状态单独地确定命令为非法的电路。 因此，通过使用掩模电路，能够防止由于具有设备和可靠性的非法命令而导致的故障。 控制电路的内在功能只能在设计和电路修改时进行验证，从而提高设计效率。