SCHEME FOR FINDING AND CHECKING WHETHER PAGE UNITS IN ONE BLOCK ARE EMPTY PAGES BY USING FLASH MEMORY DEVICE BASED ON SMALLER SEARCH RANGE

    公开(公告)号:US20240402910A1

    公开(公告)日:2024-12-05

    申请号:US18203075

    申请日:2023-05-30

    Abstract: A flash memory controller is used in a storage device and coupled to a flash memory device of the storage device through a specific communication interface and includes an input/output (I/O) circuit and a processor. The I/O circuit is used for sending commands and data between the flash memory device and the processor. The processor is used for controlling the I/O circuit sending a specific boundary check command signal or a specific boundary check set-feature signal via the specific communication interface to the flash memory device, to make the flash memory device read out more page data of multiple page units from a specific block in the memory cell array based on a smaller search range and to make the flash memory device determine whether the multiple page units are empty pages; the search range can be defined by a start page address stored in the flash memory device.

    FLASH MEMORY MECHANISM CAPABLE OF STORING AND RECORDING ACTUAL TRANSMISSION HISTORY INFORMATION OF COMMUNICATION INTERFACE BETWEEN FLASH MEMORY CONTROLLER AND FLASH MEMORY DEVICE

    公开(公告)号:US20240402942A1

    公开(公告)日:2024-12-05

    申请号:US18202962

    申请日:2023-05-29

    Abstract: A method of a flash memory device to be used in a storage device and coupled to a flash memory controller of the storage device through a specific communication interface, the flash memory device comprising an input/output (I/O) control circuit, a command register, an address register, a memory cell array at least having a first plane and a second plane which is different from the first plane, at least one address decoder, and a control circuit having a specific buffer, and the method comprises: buffering command information of a command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the command register; buffering address information of the command signal, sent from the flash memory controller and transmitted through the I/O control circuit, into the address register; and controlling the specific buffer storing a transmission history information of the specific communication interface.

    Flash memory scheme capable of automatically generating or removing dummy data portion of full page data by using flash memory device

    公开(公告)号:US12067240B2

    公开(公告)日:2024-08-20

    申请号:US17956855

    申请日:2022-09-30

    CPC classification number: G06F3/061 G06F3/0658 G06F3/0659 G06F3/0679

    Abstract: A method of a flash memory controller includes: controlling an I/O circuit using a set-feature signal, which carries a set-feature command, feature address, and parameter information, and transmitting the set-feature signal to a flash memory device; the feature address corresponds to a valid data portion or a dummy data portion following the valid data portion, and both the valid data potion and dummy data portion are comprised in a full page data which is to be written into a physical page unit of the flash memory device or to be read out from the physical page unit; the corresponding parameter information is used to record the valid data portion's column address and data length, the dummy data portion's column address and data length, the dummy data portion's column address and the valid data portion's column address, or the dummy data portion's data length and the valid data portion's data length.

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