公开(公告)号：US09431407B2

公开(公告)日：2016-08-30

申请号：US14491596

申请日：2014-09-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do ,  Jeng-Wei Yang

IPC: H01L21/00 ,  H01L21/84 ,  H01L27/115 ,  H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L21/306 ,  H01L21/762 ,  H01L21/28 ,  H01L27/12

CPC classification number: H01L27/11531 ,  H01L21/28273 ,  H01L21/30604 ,  H01L21/76224 ,  H01L21/7624 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/1207 ,  H01L29/0649 ,  H01L29/42328 ,  H01L29/66825

Abstract: A method of forming a semiconductor device starts with a substrate of silicon, a first insulation layer on the silicon, and a silicon layer on the first insulation layer. The silicon layer and the insulation layer are removed just from a second substrate area. A second insulation layer is formed over the silicon layer in the substrate first area and over the silicon in the second substrate area. A first plurality of trenches is formed in the first substrate area that each extends through all the layers and into the silicon. A second plurality of trenches is formed in the second substrate area that each extends through the second insulation layer and into the silicon. An insulation material is formed in the first and second trenches. Logic devices are formed in the first substrate area, and memory cells are formed in the second substrate area.

Abstract translation: 形成半导体器件的方法从硅衬底，硅上的第一绝缘层和第一绝缘层上的硅层开始。 仅从第二衬底区域去除硅层和绝缘层。 第二绝缘层形成在衬底第一区域中的硅层之上并且在第二衬底区域中的硅上方。 第一多个沟槽形成在第一衬底区域中，每个沟槽延伸穿过所有层并进入硅中。 第二多个沟槽形成在第二衬底区域中，每个沟槽延伸穿过第二绝缘层并进入硅中。 绝缘材料形成在第一和第二沟槽中。 逻辑器件形成在第一衬底区域中，并且存储器单元形成在第二衬底区域中。

公开(公告)号：US20150263040A1

公开(公告)日：2015-09-17

申请号：US14216553

申请日：2014-03-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Chien-Sheng Su ,  Hieu Van Tran ,  Mandana Tadayoni ,  Nhan Do

IPC: H01L27/12 ,  H01L29/66 ,  H01L27/115 ,  H01L29/788 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L27/11521 ,  H01L27/11531 ,  H01L27/1207 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7841 ,  H01L29/7881

Abstract: A semiconductor device having a silicon substrate with a first area including a buried insulation layer with silicon over and under the insulation layer and a second area in which the substrate lacks buried insulation disposed under any silicon. Logic devices are formed in the first area having spaced apart source and drain regions formed in the silicon that is over the insulation layer, and a conductive gate formed over and insulated from a portion of the silicon that is over the insulation layer and between the source and drain regions. Memory cells are formed in the second area that include spaced apart second source and second drain regions formed in the substrate and defining a channel region therebetween, a floating gate disposed over and insulated from a first portion of the channel region, and a select gate disposed over and insulated from a second portion of the channel region.

Abstract translation: 一种具有硅衬底的半导体器件，其具有第一区域，该第一区域包括在绝缘层之上和之下的具有硅的掩埋绝缘层，以及第二区域，其中衬底缺少设置在任何硅下的掩埋绝缘体。 逻辑器件形成在第一区域中，其中形成在绝缘层之上的硅中具有间隔开的源极和漏极区域，以及形成在绝缘层之上和源极之间的硅的一部分上并与其绝缘的导电栅极 和漏区。 存储单元形成在第二区域中，该第二区域包括形成在基板中的间隔开的第二源极和第二漏极区域，并且在其间限定沟道区域;布置在沟道区域的第一部分之上并与沟道区域的第一部分绝缘的浮置栅极;以及选择栅极 并且与沟道区域的第二部分绝缘。

公开(公告)号：US20140198578A1

公开(公告)日：2014-07-17

申请号：US14216776

申请日：2014-03-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Nhan Do ,  Elizabeth A. Cuevas ,  Yuri Tkachev ,  Mandana Tadayoni ,  Henry A. Om'mani

IPC: G11C16/26

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/14 ,  H01L27/115

Abstract: A method of operating a memory cell that comprises first and second regions spaced apart in a substrate with a channel region therebetween, a floating gate disposed over the channel region and the first region, a control gate disposed over the channel region and laterally adjacent to the floating gate with a portion disposed over the floating gate, and a coupling gate disposed over the first region and laterally adjacent to the floating gate. A method of erasing the memory cell includes applying a positive voltage to the control gate and a negative voltage to the coupling gate. A method of reading the memory cell includes applying positive voltages to the control gate, to the coupling gate, and to one of the first and second regions.

Abstract translation: 一种操作存储单元的方法，所述存储单元包括在衬底中间隔开的沟道区域的第一和第二区域，设置在所述沟道区域和所述第一区域上方的浮置栅极，设置在所述沟道区域上并横向邻近所述第二区域的方法 浮动栅极，其具有设置在浮置栅极上的部分，以及耦合栅极，设置在第一区域上并且横向邻近浮动栅极。 擦除存储单元的方法包括向控制栅极施加正电压，向耦合栅极施加负电压。 读取存储单元的方法包括向控制栅极，耦合栅极以及第一和第二区域之一施加正电压。