公开(公告)号：US20230411246A1

公开(公告)日：2023-12-21

申请号：US18447032

申请日：2023-08-09

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO

IPC: H01L23/48 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L23/481 ,  H01L27/0886 ,  H01L29/7851

Abstract: A semiconductor integrated circuit device includes a plurality of cells each having a fin FET. A plurality of fins constituting the fin FET extend in the X direction and are placed on virtual grid lines equally spaced in the Y direction. The cells include buried power lines: cells larges in size in the Y direction include buried power lines larger in width. The center position of each of the buried power lines in the Y direction is on a virtual grid line or at a center position between adjacent virtual grid lines.

公开(公告)号：US20220102479A1

公开(公告)日：2022-03-31

申请号：US17546463

申请日：2021-12-09

Applicant: Socionext Inc.

Inventor： Isaya SOBUE ,  Hideyuki KOMURO

IPC: H01L49/02 ,  H01L27/06

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.