公开(公告)号：US12211936B2

公开(公告)日：2025-01-28

申请号：US18146962

申请日：2022-12-27

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/15 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66

Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.

公开(公告)号：US11302812B2

公开(公告)日：2022-04-12

申请号：US17087218

申请日：2020-11-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US11133331B2

公开(公告)日：2021-09-28

申请号：US16180223

申请日：2018-11-05

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  Pierre Morin

IPC: H01L29/06 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/308 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/324 ,  H01L27/092 ,  H01L21/84 ,  H01L29/10 ,  H01L29/66 ,  H01L29/78

Abstract: A tensile strained silicon layer is patterned to form a first group of fins in a first substrate area and a second group of fins in a second substrate area. The second group of fins is covered with a tensile strained material, and an anneal is performed to relax the tensile strained silicon semiconductor material in the second group of fins and produce relaxed silicon semiconductor fins in the second area. The first group of fins is covered with a mask, and silicon-germanium material is provided on the relaxed silicon semiconductor fins. Germanium from the silicon germanium material is then driven into the relaxed silicon semiconductor fins to produce compressive strained silicon-germanium semiconductor fins in the second substrate area (from which p-channel finFET devices are formed). The mask is removed to reveal tensile strained silicon semiconductor fins in the first substrate area (from which n-channel finFET devices are formed).

公开(公告)号：US10854750B2

公开(公告)日：2020-12-01

申请号：US16680222

申请日：2019-11-11

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/00 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L27/088

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US10665497B2

公开(公告)日：2020-05-26

申请号：US15457447

申请日：2017-03-13

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES ,  STMICROELECTRONICS Inc

Inventor： Emmanuel Augendre ,  Nicolas Loubet ,  Sylvain Maitrejean ,  Pierre Morin

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L21/18 ,  H01L29/16 ,  H01L21/8238 ,  H01L29/161

Abstract: The method of manufacturing a structure comprising one or several strained semiconducting zones capable of forming one or several transistor channel regions, the method including the following steps: a) providing a substrate coated with a masking layer wherein there are one or several first slits exposing one or several first oblong semiconducting portions made of a first semiconducting material and extending in a first direction, b) making a second semiconducting material grow with a mesh parameter different from the mesh parameter of the first semiconducting material, so as to form one or several first semiconducting blocks strained along the first direction, on said one or several first oblong semiconducting portions.

公开(公告)号：US20200083376A1

公开(公告)日：2020-03-12

申请号：US16680222

申请日：2019-11-11

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US10418488B2

公开(公告)日：2019-09-17

申请号：US15677855

申请日：2017-08-15

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L29/06 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/786

Abstract: Methods and structures for forming strained-channel FETs are described. A strain-inducing layer may be formed under stress in a silicon-on-insulator substrate below the insulator. Stress-relief cuts may be formed in the strain-inducing layer to relieve stress in the strain-inducing layer. The relief of stress can impart strain to an adjacent semiconductor layer. Strained-channel, fully-depleted SOI FETs and strained-channel finFETs may be formed from the adjacent semiconductor layer. The amount and type of strain may be controlled by etch depths and geometries of the stress-relief cuts and choice of materials for the strain-inducing layer.

公开(公告)号：US10205022B2

公开(公告)日：2019-02-12

申请号：US14939729

申请日：2015-11-12

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088 ,  H01L21/02 ,  H01L29/06

Abstract: A method of making a semiconductor device includes forming a first spacer for at least one gate stack on a first semiconductor material layer, and forming a respective second spacer for each of source and drain regions adjacent the at least one gate. Each second spacer has a pair of opposing sidewalls and an end wall coupled thereto. The method includes filling the source and drain regions with a second semiconductor material while the first and second spacers provide confinement.

公开(公告)号：US10037922B2

公开(公告)日：2018-07-31

申请号：US15874813

申请日：2018-01-18

Applicant: STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/417 ,  H01L29/78

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20170200653A1

公开(公告)日：2017-07-13

申请号：US15469851

申请日：2017-03-27

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L21/8238 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L21/823821 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/41791 ,  H01L29/4916 ,  H01L29/7842 ,  H01L29/785

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.