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16 条记录 (耗时 0.11 秒)

    INSTRUCTION FILTERING
    11.
    发明申请
    INSTRUCTION FILTERING 有权
    指令过滤

    公开(公告)号：US20130339683A1

    公开(公告)日：2013-12-19

    申请号：US13523170

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

    摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

    摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

    Clock-based debugging for embedded dynamic random access memory element in a processor core
    12.
    发明授权
    Clock-based debugging for embedded dynamic random access memory element in a processor core 失效
    基于时钟的调试，用于处理器内核中的嵌入式动态随机存取存储器元件

    公开(公告)号：US08495287B2

    公开(公告)日：2013-07-23

    申请号：US12822882

    申请日：2010-06-24

    申请人： Adam B. Collura ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Gerard M. Salem ,  Robert J. Sonnelitter, III

    发明人： Adam B. Collura ,  Michael Fee ,  Arthur J. O'Neill, Jr. ,  Gerard M. Salem ,  Robert J. Sonnelitter, III

    IPC分类号： G06F12/08 ,  G06F12/16

    CPC分类号： G06F11/073 ,  G06F11/0751

    摘要： A method of debugging an embedded dynamic random access memory (eDRAM) element of a processor core is provided. An aspect includes, based on an error occurring in the eDRAM element, stopping a functional clock, and not stopping a refresh clock. Another aspect includes, based on the functional clock being stopped, creating a fence signal that prevents all commands other than a refresh command, the refresh command being based on the refresh clock, from entering into the eDRAM element. Another aspect includes initializing a line fetch controller of the processor core with at least one of write data and read data. Another aspect includes restarting the functional clock. Another aspect includes performing at least one of write requests and read requests to the eDRAM element based on the at least one of the write data and the read data from the line fetch controller based on the functional clock.

    摘要翻译： 提供了一种调试处理器核心的嵌入式动态随机存取存储器（eDRAM）元件的方法。 一个方面包括基于eDRAM元件中发生的错误，停止功能时钟，而不是停止刷新时钟。 另一方面包括基于停止的功能时钟，创建围栏信号，该屏障信号防止刷新命令以外的所有命令（刷新命令基于刷新时钟）进入eDRAM元素。 另一方面包括用写入数据和读取数据中的至少一个初始化处理器核心的线取指控制器。 另一方面包括重启功能时钟。 另一方面包括基于功能时钟，基于来自线取指控制器的写入数据和读取数据中的至少一个，向eDRAM元件执行至少一个写入请求和读取请求。

    Instruction filtering
    14.
    发明授权
    Instruction filtering 有权
    指令过滤

    公开(公告)号：US09135012B2

    公开(公告)日：2015-09-15

    申请号：US13523170

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

    摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

    摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

    CACHE LINE HISTORY TRACKING USING AN INSTRUCTION ADDRESS REGISTER FILE
    15.
    发明申请
    CACHE LINE HISTORY TRACKING USING AN INSTRUCTION ADDRESS REGISTER FILE 有权
    使用指令地址寄存器文件进行高速缓存行历史跟踪

    公开(公告)号：US20130339610A1

    公开(公告)日：2013-12-19

    申请号：US13523686

    申请日：2012-06-14

    申请人： Adam B. Collura ,  Brian R. Prasky

    发明人： Adam B. Collura ,  Brian R. Prasky

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0811 ,  G06F9/38 ,  G06F9/3824 ,  G06F11/34 ,  G06F11/3471 ,  G06F12/0802 ,  G06F2201/885

    摘要： Embodiments relate to tracking cache lines. An aspect of embodiments includes performing an operation by a processor. Another aspect of embodiments includes fetching a cache line based on the operation. Yet another aspect of embodiments includes storing in an instruction address register file at least one of (i) an operation identifier identifying the operation and (ii) a memory location identifier identifying a level of memory from which the cache line is populated.

    摘要翻译： 实施例涉及跟踪高速缓存行。 实施例的一个方面包括执行处理器的操作。 实施例的另一方面包括基于该操作获取高速缓存行。 实施例的另一方面包括在指令地址寄存器文件中存储以下至少一个：（i）识别操作的操作标识符和（ii）识别高速缓存线从其填充的存储器级别的存储器位置标识符。