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    ERROR DETECTION AND RECOVERY IN A SHARED PIPELINE
    3.
    发明申请
    ERROR DETECTION AND RECOVERY IN A SHARED PIPELINE 失效
    在共享管道中的错误检测和恢复

    公开(公告)号：US20110320855A1

    公开(公告)日：2011-12-29

    申请号：US12821871

    申请日：2010-06-23

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F11/07

    CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/0793

    摘要： A pipelined processing device includes: a processor configured to receive a request to perform an operation; a plurality of processing controllers configured to receive at least one instruction associated with the operation, each of the plurality of processing controllers including a memory to store at least one instruction therein; a pipeline processor configured to receive and process the at least one instruction, the pipeline processor including shared error detection logic configured to detect a parity error in the at least one instruction as the at least one instruction is processed in a pipeline and generate an error signal; and a pipeline bus connected to each of the plurality of processing controllers and configured to communicate the error signal from the error detection logic.

    摘要翻译： 流水线处理装置包括：被配置为接收执行操作的请求的处理器; 多个处理控制器，被配置为接收与所述操作相关联的至少一个指令，所述多个处理控制器中的每个处理控制器包括用于在其中存储至少一个指令的存储器; 流水线处理器，被配置为接收和处理所述至少一个指令，所述流水线处理器包括被配置为在流水线中处理所述至少一个指令时检测所述至少一个指令中的奇偶校验错误的共享错误检测逻辑，并且生成错误信号 ; 以及连接到所述多个处理控制器中的每个处理控制器并被配置为传送来自所述错误检测逻辑的所述错误信号的流水线总线。

    EDRAM REFRESH IN A HIGH PERFORMANCE CACHE ARCHITECTURE
    4.
    发明申请
    EDRAM REFRESH IN A HIGH PERFORMANCE CACHE ARCHITECTURE 有权
    EDRAM在高性能缓存架构中刷新

    公开(公告)号：US20110320696A1

    公开(公告)日：2011-12-29

    申请号：US12822245

    申请日：2010-06-24

    申请人： Michael Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

    发明人： Michael Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

    IPC分类号： G06F12/08 ,  G06F12/02

    CPC分类号： G06F12/0893 ,  G06F13/14 ,  G06F13/16 ,  G06F13/1605 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40618 ,  G11C2207/104

    摘要： A memory refresh requestor, a memory request interpreter, a cache memory, and a cache controller on a single chip. The cache controller configured to receive a memory access request, the memory access request for a memory address range in the cache memory, detect that the cache memory located at the memory address range is available, and send the memory access request to the memory request interpreter when the memory address range is available. The memory request interpreter configured to receive the memory access request from the cache controller, determine if the memory access request is a request to refresh a contents of the memory address range, and refresh data in the memory address range when the memory access request is a request to refresh memory.

    摘要翻译： 在单个芯片上的存储器刷新请求器，存储器请求解释器，高速缓存存储器和高速缓存控制器。 缓存控制器被配置为接收存储器访问请求，对高速缓冲存储器中的存储器地址范围的存储器访问请求，检测位于存储器地址范围的高速缓存存储器可用，并将存储器访问请求发送到存储器请求解释器 当存储器地址范围可用时。 存储器请求解释器被配置为从高速缓存控制器接收存储器访问请求，确定存储器访问请求是否是刷新存储器地址范围的内容的请求，以及当存储器访问请求是存储器访问请求时刷新存储器地址范围中的数据 请求刷新内存。

    SYSTEM AND METHOD FOR MANAGING DATAFLOW IN A TEMPORARY MEMORY
    5.
    发明申请
    SYSTEM AND METHOD FOR MANAGING DATAFLOW IN A TEMPORARY MEMORY 失效
    用于管理临时存储器中的数据流的系统和方法

    公开(公告)号：US20110314183A1

    公开(公告)日：2011-12-22

    申请号：US12820589

    申请日：2010-06-22

    申请人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    发明人： Ekaterina M. Ambroladze ,  Deanna Postles Dunn Berger ,  Michael Fee ,  Arthur J. O'Neill, JR. ,  Diana Lynn Orf ,  Robert J. Sonnelitter, III

    IPC分类号： G06F3/00 ,  G06F5/14

    CPC分类号： G06F11/0751 ,  G06F11/0724 ,  G06F11/073 ,  G06F12/0897 ,  Y02D10/13

    摘要： A method of managing a temporary memory includes: receiving a request to transfer data from a source location to a destination location, the data transfer request associated with an operation to be performed, the operation selected from an input into an intermediate temporary memory and an output; checking a two-state indicator associated with the temporary memory, the two-state indicator having a first state indicating that an immediately preceding operation on the temporary memory was an input to the temporary memory and a second state indicating that the immediately preceding operation was an output from the temporary memory; and performing the operation responsive to one of: the operation being an input operation and the two-state indicator being in the second state, indicating that the immediately preceding operation was an output; and the operation being an output operation and the two-state indicator being in the first state, indicating that the immediately preceding operation was an input.

    摘要翻译： 管理临时存储器的方法包括：接收从源位置传送数据到目的地位置的请求，与要执行的操作相关联的数据传输请求，从输入中选择的中间临时存储器和输出 ; 检查与临时存储器相关联的两状态指示符，两状态指示符具有指示临时存储器上的紧接在前的操作是临时存储器的输入的第一状态，以及指示紧接在前的操作是第二状态的第二状态 从临时存储器输出; 并且响应于以下操作中的一个执行操作：作为输入操作的操作和处于第二状态的两状态指示器，指示紧接在前的操作是输出; 操作是输出操作，两状态指示灯处于第一状态，表示紧接在前的操作是输入。

    PERFORMANCE OPTIMIZATION AND DYNAMIC RESOURCE RESERVATION FOR GUARANTEED COHERENCY UPDATES IN A MULTI-LEVEL CACHE HIERARCHY
    8.
    发明申请
    PERFORMANCE OPTIMIZATION AND DYNAMIC RESOURCE RESERVATION FOR GUARANTEED COHERENCY UPDATES IN A MULTI-LEVEL CACHE HIERARCHY 失效
    性能优化和动态资源预留在多层次高速缓存中进行保守的更新

    公开(公告)号：US20110320728A1

    公开(公告)日：2011-12-29

    申请号：US12821726

    申请日：2010-06-23

    申请人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

    发明人： Deanna Postles Dunn Berger ,  Michael F. Fee ,  Arthur J. O'Neill, JR. ,  Robert J. Sonnelitter, III

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0831 ,  G06F12/0811

    摘要： A cache includes a cache pipeline, a request receiver configured to receive off chip coherency requests from an off chip cache and a plurality of state machines coupled to the request receiver. The cache also includes an arbiter coupled between the plurality of state machines and the cache pipe line and is configured to give priority to off chip coherency requests as well as a counter configured to count the number of coherency requests sent from the cache pipeline to a lower level cache. The cache pipeline is halted from sending coherency requests when the counter exceeds a predetermined limit.

    摘要翻译： 高速缓存包括高速缓存流水线，被配置为从芯片内高速缓存和多个与所述请求接收器耦合的状态机接收芯片外相关性请求的请求接收器。 高速缓存还包括耦合在多个状态机和高速缓存管线之间的仲裁器，并且被配置为优先考虑片外一致性请求，以及被配置为将从高速缓存流水线发送的一致性请求的数量计数到较低 级缓存。 当计数器超过预定限制时，高速缓存流水线停止发送一致性请求。

    DYNAMIC PIPELINE CACHE ERROR CORRECTION
    9.
    发明申请
    DYNAMIC PIPELINE CACHE ERROR CORRECTION 失效
    动态管道缓存错误校正

    公开(公告)号：US20110320866A1

    公开(公告)日：2011-12-29

    申请号：US12822437

    申请日：2010-06-24

    申请人： Ekaterina M. Ambroladze ,  Michael Fee ,  Edward T. Gerchman ,  Arthur J. O'Neill, JR.

    发明人： Ekaterina M. Ambroladze ,  Michael Fee ,  Edward T. Gerchman ,  Arthur J. O'Neill, JR.

    IPC分类号： G06F11/14

    CPC分类号： G06F11/1048

    摘要： Dynamic pipeline cache error correction includes receiving a request to perform an operation that requires a storage cache slot, the storage cache slot residing in a cache. The dynamic pipeline cache error correction also includes accessing the storage cache slot, determining a cache hit for the storage cache slot, identifying and correcting any correctable soft errors associated with the storage cache slot. The dynamic cache error correction further includes updating the cache with results of corrected data.

    摘要翻译： 动态流水线高速缓存错误校正包括接收执行需要存储高速缓存时隙的操作的请求，存储高速缓冲存储器时隙驻留在高速缓存中。 动态流水线高速缓存错误校正还包括访问存储高速缓存时隙，确定存储高速缓存时隙的高速缓存命中，识别和校正与存储高速缓存槽相关联的任何可校正的软错误。 动态高速缓存错误校正还包括用校正数据的结果更新高速缓存。

    METHOD FOR OPTIMIZING SEQUENTIAL DATA FETCHES IN A COMPUTER SYSTEM
    10.
    发明申请
    METHOD FOR OPTIMIZING SEQUENTIAL DATA FETCHES IN A COMPUTER SYSTEM 失效
    在计算机系统中优化顺序数据电位的方法

    公开(公告)号：US20110320740A1

    公开(公告)日：2011-12-29

    申请号：US12822486

    申请日：2010-06-24

    申请人： Ekaterina M. Ambroladze ,  Michael Fee ,  Arthur J. O'Neill, JR.

    发明人： Ekaterina M. Ambroladze ,  Michael Fee ,  Arthur J. O'Neill, JR.

    IPC分类号： G06F12/08

    CPC分类号： G06F12/1408 ,  G06F12/0802

    摘要： A computer implemented method of optimizing sequential data fetches in a computer system is provided. The method includes fetching a data segment from a main memory, the data segment having a plurality of target data entries; extracting a first portion of the data segment and storing the first portion into a target data cache, the first portion having a first target data entry; and storing the data segment into an intermediate cache line buffer in communication with the target data cache to enable subsequent fetches to a number target data entries in the data segment.

    摘要翻译： 提供了一种在计算机系统中优化顺序数据提取的计算机实现的方法。 该方法包括从主存储器获取数据段，该数据段具有多个目标数据条目; 提取所述数据段的第一部分并将所述第一部分存储到目标数据高速缓存中，所述第一部分具有第一目标数据条目; 以及将数据段存储到与目标数据高速缓存通信的中间高速缓存行缓冲器中，以便能够随后提取数据段中的数目目标数据条目。