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    Cache set selective power up
    2.
    发明授权
    Cache set selective power up 有权
    缓存设置选择上电

    公开(公告)号：US08972665B2

    公开(公告)日：2015-03-03

    申请号：US13524574

    申请日：2012-06-15

    申请人： Brian R. Prasky ,  Anthony Saporito ,  Aaron Tsai

    发明人： Brian R. Prasky ,  Anthony Saporito ,  Aaron Tsai

    IPC分类号： G06F1/32 ,  G06F21/81 ,  G06F17/30

    CPC分类号： G06F1/3275 ,  G06F9/3802 ,  G06F12/0864 ,  G06F17/30982 ,  G06F2212/1028 ,  G06F2212/6082 ,  Y02D10/13

    摘要： Embodiments of the disclosure include selectively powering up a cache set of a multi-set associative cache by receiving an instruction fetch address and determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory. Based on determining that the instruction fetch address corresponds to one of a plurality of entries of a content addressable memory a cache set of the multi-set associative cache that contains a cache line referenced by the instruction fetch address is identified and only powering up a subset of cache. Based on the identified cache set not being powered up, selectively powering up the identified cache set of the multi-set associative cache and transmitting one or more instructions stored in the cache line referenced by the instruction fetch address to a processor.

    摘要翻译： 本公开的实施例包括通过接收指令获取地址并且确定指令获取地址对应于内容可寻址存储器的多个条目之一来选择性地加电多组关联高速缓存的高速缓存组。 基于确定指令获取地址对应于内容可寻址存储器的多个条目中的一个，识别包含由指令获取地址引用的高速缓存行的多组关联高速缓存的高速缓存集，并且仅为子集 的缓存。 基于所识别的未被加电的高速缓存集，选择性地加电多组关联高速缓存的所识别的高速缓存集，并且将由指令提取地址引用的高速缓存行中存储的一个或多个指令发送到处理器。

    Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs
    3.
    发明授权
    Mitigating lookahead branch prediction latency by purposely stalling a branch instruction until a delayed branch prediction is received or a timeout occurs 有权
    通过故意停止分支指令，直到接收到延迟的分支预测或发生超时来减轻前瞻分支预测等待时间

    公开(公告)号：US08874885B2

    公开(公告)日：2014-10-28

    申请号：US12029543

    申请日：2008-02-12

    申请人： James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

    发明人： James J. Bonanno ,  David S. Hutton ,  Brian R. Prasky ,  Anthony Saporito

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3844 ,  G06F9/3806 ,  G06F9/3836 ,  G06F9/3848

    摘要： Embodiments relate to mitigation of lookahead branch predication latency. An aspect includes receiving an instruction address in an instruction cache for fetching instructions in a microprocessor pipeline. Another aspect includes receiving the instruction address in a branch presence predictor coupled to the microprocessor pipeline. Another aspect includes determining, by the branch presence predictor, presence of a branch instruction in the instructions being fetched, wherein the branch instruction is predictable by the branch target buffer, and any indication of the instruction address not written to the branch target buffer is also not written to the branch presence predictor. Another aspect includes, based on receipt of an indication that the branch instruction is present from the branch presence predictor, holding the branch instruction. Another aspect includes, based on receipt of a branch prediction corresponding to the branch instruction from the branch target buffer, releasing said held branch instruction to the pipeline.

    摘要翻译： 实施例涉及减轻前瞻分支预测延迟。 一个方面包括在指令高速缓存中接收用于在微处理器流水线中取指令的指令地址。 另一方面包括在耦合到微处理器流水线的分支存在预测器中接收指令地址。 另一方面包括通过分支存在预测器确定在所取出的指令中存在分支指令，其中分支指令可由分支目标缓冲器预测，并且未写入分支目标缓冲器的指令地址的任何指示也是 没有写入分支存在预测器。 另一方面包括：基于从分支存在预测器接收到分支指令的指示，保持分支指令。 另一方面包括基于从分支目标缓冲器接收到与分支指令相对应的分支预测，将所述保持的分支指令释放到流水线。

    SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION
    4.
    发明申请
    SELECTIVELY BLOCKING BRANCH INSTRUCTION PREDICTION 有权
    选择性阻塞分支指导预测

    公开(公告)号：US20130339696A1

    公开(公告)日：2013-12-19

    申请号：US13524402

    申请日：2012-06-15

    申请人： James J. Bonanno ,  Ulrich Mayer ,  Anthony Saporito ,  Chung-Lung K. Shum ,  Timothy J. Slegel

    发明人： James J. Bonanno ,  Ulrich Mayer ,  Anthony Saporito ,  Chung-Lung K. Shum ,  Timothy J. Slegel

    IPC分类号： G06F9/38

    CPC分类号： G06F9/38 ,  G06F9/30076 ,  G06F9/3844 ,  G06F9/3848

    摘要： Embodiments relate to selectively blocking branch instruction predictions. An aspect includes a computer system for performing selective branch prediction. The system includes memory and a processor, and the system is configured to perform a method. The method includes detecting a branch-prediction blocking instruction in a stream of instructions and blocking branch prediction of a predetermined number of branch instructions following the branch-prediction blocking instruction based on the detecting the branch-prediction blocking instruction.

    摘要翻译： 实施例涉及选择性地阻止分支指令预测。 一个方面包括用于执行选择性分支预测的计算机系统。 系统包括存储器和处理器，并且系统被配置为执行方法。 该方法包括：根据检测分支预测阻断指令，在分支预测阻塞指令之后检测指令流中的分支预测分块指令并阻止预分支数量的分支指令的分支预测。

    Method, system and computer program product for an implicit predicted return from a predicted subroutine
    5.
    发明授权
    Method, system and computer program product for an implicit predicted return from a predicted subroutine 失效
    用于预测子程序的隐式预测回报的方法，系统和计算机程序产品

    公开(公告)号：US07882338B2

    公开(公告)日：2011-02-01

    申请号：US12034066

    申请日：2008-02-20

    申请人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito, III ,  Robert J. Sonnelitter, III ,  Charles F. Webb

    发明人： Khary J. Alexander ,  James J. Bonanno ,  Brian R. Prasky ,  Anthony Saporito, III ,  Robert J. Sonnelitter, III ,  Charles F. Webb

    IPC分类号： G06F9/32

    CPC分类号： G06F9/30054 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3844

    摘要： A method, system and computer program product for performing an implicit predicted return from a predicted subroutine are provided. The system includes a branch history table/branch target buffer (BHT/BTB) to hold branch information, including a target address of a predicted subroutine and a branch type. The system also includes instruction buffers, and instruction fetch controls to perform a method including fetching a branch instruction at a branch address and a return-point instruction. The method also includes receiving the target address and the branch type, and fetching a fixed number of instructions in response to the branch type. The method further includes referencing the return-point instruction within the instruction buffers such that the return-point instruction is available upon completing the fetching of the fixed number of instructions absent a re-fetch of the return-point instruction.

    摘要翻译： 提供了一种用于从预测子程序执行隐含预测返回的方法，系统和计算机程序产品。 该系统包括用于保持分支信息的分支历史表/分支目标缓冲器（BHT / BTB），包括预测子程序的目标地址和分支类型。 该系统还包括指令缓冲器和指令获取控制，以执行包括在分支地址和返回点指令处获取分支指令的方法。 该方法还包括接收目标地址和分支类型，以及响应于分支类型取出固定数目的指令。 该方法还包括引用指令缓冲器内的返回点指令，使得在没有重新获取返回点指令的情况下完成取出固定数目的指令后，返回点指令是可用的。

    System and method for Controlling restarting of instruction fetching using speculative address computations
    8.
    发明授权
    System and method for Controlling restarting of instruction fetching using speculative address computations 有权
    使用推测地址计算控制指令重写的系统和方法

    公开(公告)号：US09021240B2

    公开(公告)日：2015-04-28

    申请号：US12035911

    申请日：2008-02-22

    申请人： Khary J. Alexander ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

    发明人： Khary J. Alexander ,  Brian R. Prasky ,  Anthony Saporito ,  Robert J. Sonnelitter, III

    IPC分类号： G06F9/38 ,  G06F9/32

    CPC分类号： G06F9/3861 ,  G06F9/322 ,  G06F9/3804 ,  G06F9/3806 ,  G06F9/3838 ,  G06F9/3842 ,  G06F9/3867

    摘要： A system and method for controlling restarting of instruction fetching using speculative address computations in a processor are provided. The system includes a predicted target queue to hold branch prediction logic (BPL) generated target address values. The system also includes target selection logic including a recycle queue. The target selection logic selects a saved branch target value between a previously speculatively calculated branch target value from the recycle queue and an address value from the predicted target queue. The system further includes a compare block to identify a wrong target in response to a mismatch between the saved branch target value and a current calculated branch target, where instruction fetching is restarted in response to the wrong target.

    摘要翻译： 提供了一种用于使用处理器中的推测地址计算来控制重新启动指令取出的系统和方法。 该系统包括预测的目标队列以保持分支预测逻辑（BPL）生成的目标地址值。 系统还包括目标选择逻辑，包括循环队列。 目标选择逻辑从先前推测计算出的来自再循环队列的分支目标值和来自预测目标队列的地址值之间选择保存的分支目标值。 系统还包括比较块，用于响应于所保存的分支目标值与当前计算的分支目标之间的不匹配来识别错误的目标，其中响应于错误的目标重新启动指令获取。

    INSTRUCTION FILTERING
    9.
    发明申请
    INSTRUCTION FILTERING 有权
    指令过滤

    公开(公告)号：US20130339683A1

    公开(公告)日：2013-12-19

    申请号：US13523170

    申请日：2012-06-14

    申请人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    发明人： James J. Bonanno ,  Adam B. Collura ,  Ulrich Mayer ,  Brian R. Prasky ,  Anthony Saporito ,  Chung-Lung K. Shum

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3844 ,  G06F9/30 ,  G06F9/30047 ,  G06F9/3005 ,  G06F9/3806 ,  G06F9/3836

    摘要： Embodiments relate to instruction filtering. An aspect includes a system for instruction filtering. The system includes memory configured to store instructions accessible by a processor, and the processor includes a tracking array and a tracked instruction logic block. The processor is configured to perform a method including detecting a tracked instruction in an instruction stream, and storing an instruction address of the tracked instruction in the tracking array based on detecting and executing the tracked instruction. The method also includes accessing the tracking array based on an address of instruction data of a subsequently fetched instruction to locate the instruction address of the tracked instruction in the tracking array as an indication of the tracked instruction. Instruction text of the subsequently fetched instruction is marked to indicate previous execution based on the tracking array. An action of the tracked instruction logic block is prevented based on the marked instruction text.

    摘要翻译： 实施例涉及指令过滤。 一个方面包括用于指令过滤的系统。 该系统包括被配置为存储由处理器可访问的指令的存储器，并且处理器包括跟踪阵列和跟踪的指令逻辑块。 处理器被配置为执行包括检测指令流中的跟踪指令并且基于检测和执行跟踪指令将追踪指令的指令地址存储在跟踪数组中的方法。 该方法还包括基于随后获取的指令的指令数据的地址来访问跟踪数组，以将跟踪数组中跟踪的指令的指令地址定位为跟踪指令的指示。 随后获取的指令的指令文本被标记为基于跟踪数组指示先前的执行。 基于标记的指令文本来防止跟踪指令逻辑块的动作。

    Method, apparatus and program product for enhancing performance of an in-order processor with long stalls
    10.
    发明授权
    Method, apparatus and program product for enhancing performance of an in-order processor with long stalls 失效
    用于提高具有长档位的处理器性能的方法，装置和程序产品

    公开(公告)号：US07603543B2

    公开(公告)日：2009-10-13

    申请号：US11055862

    申请日：2005-02-11

    申请人： Miles Robert Dooley ,  Scott Bruce Frommer ,  Hung Qui Le ,  Sheldon B. Levenstein ,  Anthony Saporito

    发明人： Miles Robert Dooley ,  Scott Bruce Frommer ,  Hung Qui Le ,  Sheldon B. Levenstein ,  Anthony Saporito

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3867

    摘要： A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes.

    摘要翻译： 一种方法，系统和计算机程序产品，用于增强具有长档位的按顺序微处理器的性能。 特别地，本发明的机构提供了一种用于在处理器内存储数据的数据结构。 本发明的机构包括包括由处理器使用的信息的数据结构。 数据结构包括一组比特，用于跟踪被拒绝指令之前的哪些指令，因此将被允许完成，以及哪些指令遵循被拒绝的指令。 该比特组包括指示拒绝是否是快速或慢速拒绝的位; 以及表示通过管道的指令的状态的每个周期的一点。 处理器推测地在停滞时段期间继续执行设置位的相应指令，以便产生在停滞期结束并且恢复正常调度时将需要的地址。