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公开(公告)号：US09208857B2
公开(公告)日：2015-12-08
申请号：US14266457
申请日：2014-04-30
发明人： Yi-Tzu Chen , Wei-jer Hsieh , Tsai-Hsin Lai , Ling-Fang Hsu , Hau-Tai Shieh
IPC分类号： G11C7/10 , G11C11/418 , G11C11/413 , G11C7/18
CPC分类号： G11C11/418 , G11C7/1012 , G11C7/18 , G11C11/413
摘要： An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.
摘要翻译： SRAM多路复用装置包括多个本地多路复用器和全局多路复用器。 每个本地多路复用器耦合到存储体。 全局多路复用器具有多个输入，每个输入耦合到多个本地多路复用器的相应输出端。 响应于读操作中的解码地址，本地多路复用器的输入被转发到全局多路复用器的相应输入端。 类似地，解码的地址允许全局多路复用器经由缓冲器将输入信号转发到数据输出端口。
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公开(公告)号：US20240201232A1
公开(公告)日：2024-06-20
申请号：US18587508
申请日：2024-02-26
发明人： Chia-Chen Kuo , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： G01R19/165 , H02H1/00 , H02H9/02
CPC分类号： G01R19/16519 , G01R19/16538 , H02H1/0007 , H02H9/02
摘要： A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
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公开(公告)号：US20230204634A1
公开(公告)日：2023-06-29
申请号：US18178900
申请日：2023-03-06
发明人： Chia-Chen Kuo , Chiting Cheng , Wei-jer Hsieh , Yangsyu Lin
IPC分类号： G01R19/165 , H02H1/00 , H02H9/02
CPC分类号： G01R19/16519 , G01R19/16538 , H02H1/0007 , H02H9/02
摘要： A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
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公开(公告)号：US20220328097A1
公开(公告)日：2022-10-13
申请号：US17850354
申请日：2022-06-27
发明人： Wei-jer Hsieh , Chiting Cheng , Yangsyu Lin , Shang-Chi Wu
IPC分类号： G11C11/419 , G11C7/12 , G11C11/408 , G11C11/4096 , H01L23/522 , G11C8/08
摘要： A write assist circuit is provided. The write assist circuit includes a transistor switch coupled between a bit line voltage node of a cell array and a ground node. An invertor is operative to receive a boost signal responsive to a write enable signal. An output of the invertor is coupled to a gate of the transistor switch. The write assist circuit further includes a capacitor having a first end coupled to the bit line voltage node and a second end coupled to the gate node. The capacitor is operative to drive a bit line voltage of the bit line voltage node to a negative value from the ground voltage in response to the boost signal.
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公开(公告)号：US20140233303A1
公开(公告)日：2014-08-21
申请号：US14266457
申请日：2014-04-30
发明人： Yi-Tzu Chen , Wei-jer Hsieh , Tsai-Hsin Lai , Ling-Fang Hsu , Hau-Tai Shieh
IPC分类号： G11C11/418
CPC分类号： G11C11/418 , G11C7/1012 , G11C7/18 , G11C11/413
摘要： An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.
摘要翻译： SRAM多路复用装置包括多个本地多路复用器和全局多路复用器。 每个本地多路复用器耦合到存储体。 全局多路复用器具有多个输入，每个输入耦合到多个本地多路复用器的相应输出端。 响应于读操作中的解码地址，本地多路复用器的输入被转发到全局多路复用器的相应输入端。 类似地，解码的地址允许全局多路复用器经由缓冲器将输入信号转发到数据输出端口。
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