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    Sub-Word Line Driver Placement For Memory Device
    1.
    发明公开
    Sub-Word Line Driver Placement For Memory Device 审中-公开

    公开(公告)号：US20240185911A1

    公开(公告)日：2024-06-06

    申请号：US18443979

    申请日：2024-02-16

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

    IPC分类号： G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093

    CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

    摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

    Sub-Word Line Driver Placement For Memory Device
    2.
    发明公开
    Sub-Word Line Driver Placement For Memory Device 审中-公开

    公开(公告)号：US20230267989A1

    公开(公告)日：2023-08-24

    申请号：US18306762

    申请日：2023-04-25

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

    IPC分类号： G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093

    CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

    摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.

    Data-aware SRAM systems and methods forming same
    6.
    发明授权
    Data-aware SRAM systems and methods forming same 有权
    数据感知SRAM系统和方法形成

    公开(公告)号：US09058899B2

    公开(公告)日：2015-06-16

    申请号：US14083249

    申请日：2013-11-18

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Chien-Yuan Chen ,  Yi-Tzu Chen ,  Hau-Tai Shieh ,  Tsung-Yung Jonathan Chang

    IPC分类号： G11C11/00 ,  G11C11/417 ,  G11C11/412 ,  G11C11/413

    CPC分类号： G11C11/417 ,  G11C11/412 ,  G11C11/413

    摘要： Exemplary embodiments for SRAM cells, new control units for SRAM systems, and embodiments of SRAM systems are described herein. An SRAM cell is configured to receive a first input voltage signal and a second input voltage signal with a different value from the first input voltage signal, and to maintain a first stored value signal and a second stored value signal. A control circuit is configured to receive a first input voltage signal and a second input voltage signal, and controlled by a sleep signal, a selection signal, and a data input signal, so that the output of the control circuit is data sensitive to the data input signal. An SRAM system comprises a plurality of SRAM cells, controlled the disclosed control circuit wherein an SRAM cell has two input voltage signals controlled by a data input signal and its complement signal respectively.

    摘要翻译： SRAM单元的示例性实施例，用于SRAM系统的新的控制单元以及SRAM系统的实施例在此被描述。 SRAM单元被配置为接收具有与第一输入电压信号不同的值的第一输入电压信号和第二输入电压信号，并且保持第一存储值信号和第二存储值信号。 控制电路被配置为接收第一输入电压信号和第二输入电压信号，并且由睡眠信号，选择信号和数据输入信号控制，使得控制电路的输出对数据是敏感的 输入信号。 SRAM系统包括多个SRAM单元，控制所公开的控制电路，其中SRAM单元分别具有由数据输入信号及其补码信号控制的两个输入电压信号。

    SRAM Multiplexing Apparatus
    7.
    发明申请
    SRAM Multiplexing Apparatus 审中-公开
    SRAM复用器

    公开(公告)号：US20140233303A1

    公开(公告)日：2014-08-21

    申请号：US14266457

    申请日：2014-04-30

    申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

    发明人： Yi-Tzu Chen ,  Wei-jer Hsieh ,  Tsai-Hsin Lai ,  Ling-Fang Hsu ,  Hau-Tai Shieh

    IPC分类号： G11C11/418

    CPC分类号： G11C11/418 ,  G11C7/1012 ,  G11C7/18 ,  G11C11/413

    摘要： An SRAM multiplexing apparatus comprise a plurality of local multiplexers and a global multiplexer. Each local multiplexer is coupled to a memory bank. The global multiplexer has a plurality of inputs, each of which is coupled to a corresponding output of the plurality of local multiplexers. In response to a decoded address in a read operation, an input of a local multiplexer is forwarded to a corresponding input of the global multiplexer. Similarly, the decoded address allows the global multiplexer to forward the input signal to a data out port via a buffer.

    摘要翻译： SRAM多路复用装置包括多个本地多路复用器和全局多路复用器。 每个本地多路复用器耦合到存储体。 全局多路复用器具有多个输入，每个输入耦合到多个本地多路复用器的相应输出端。 响应于读操作中的解码地址，本地多路复用器的输入被转发到全局多路复用器的相应输入端。 类似地，解码的地址允许全局多路复用器经由缓冲器将输入信号转发到数据输出端口。

    Sub-word line driver placement for memory device
    8.
    发明授权
    Sub-word line driver placement for memory device 有权

    公开(公告)号：US11670362B2

    公开(公告)日：2023-06-06

    申请号：US17687272

    申请日：2022-03-04

    申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

    发明人： Yi-Tzu Chen ,  Ching-Wei Wu ,  Hau-Tai Shieh ,  Hung-Jen Liao

    IPC分类号： G11C11/40 ,  G11C11/408 ,  G11C5/02 ,  G11C5/06 ,  G11C11/4093

    CPC分类号： G11C11/4085 ,  G11C5/025 ,  G11C5/06 ,  G11C11/4093

    摘要： Disclosed herein are related to a memory system including unit storage circuits. In one aspect, each of the unit storage circuits abuts an adjacent one of the unit storage circuits. In one aspect, each of the unit storage circuits includes a first group of memory cells, a second group of memory cells, a first sub-word line driver to apply a first control signal to the first group of memory cells through a first sub-word line extending along a direction, and a second sub-word line driver to apply a second control signal to the second group of memory cells through a second sub-word line extending along the direction. In one aspect, the memory system includes a common word line driver abutting one of the unit storage circuits and configured to apply a common control signal to the unit storage circuits through a word line extending along the direction.