公开(公告)号：US20210073454A1

公开(公告)日：2021-03-11

申请号：US16950999

申请日：2020-11-18

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ke-Ying SU ,  Jon-Hsu HO ,  Ke-Wei SU ,  Liang-Yi CHEN ,  Wen-Hsing HSIEH ,  Wen-Koi LAI ,  Keng-Hua KUO ,  KuoPei LU ,  Lester CHANG ,  Ze-Ming WU

IPC分类号： G06F30/398 ,  G03F1/70 ,  G03F1/36 ,  G06F30/20

摘要： A method of generating a netlist of an IC device includes receiving gate region information of the IC device. The gate region information includes a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, a location of a gate via positioned within the active region and along the width, and a first gate resistance value corresponding to the gate region. The method includes determining a second gate resistance value based on the location and the width, and modifying the netlist based on the second gate resistance value.

公开(公告)号：US20240160828A1

公开(公告)日：2024-05-16

申请号：US18421644

申请日：2024-01-24

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ke-Ying SU ,  Jon-Hsu HO ,  Ke-Wei SU ,  Liang-Yi CHEN ,  Wen-Hsing HSIEH ,  Wen-Koi LAI ,  Keng-Hua KUO ,  KuoPei LU ,  Lester CHANG ,  Ze-Ming WU

IPC分类号： G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G06F30/20

CPC分类号： G06F30/398 ,  G03F1/36 ,  G03F1/70 ,  G06F30/20

摘要： A method of generating an IC layout diagram includes receiving an IC layout diagram including a gate region and a gate via, the gate via being positioned at a location within an active region and along a width of the gate region extending across the active region, receiving a first gate resistance value of the gate region, retrieving a second gate resistance value from a resistance value reference based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

公开(公告)号：US20220343054A1

公开(公告)日：2022-10-27

申请号：US17860919

申请日：2022-07-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Ke-Ying SU ,  Jon-Hsu HO ,  Ke-Wei SU ,  Liang-Yi CHEN ,  Wen-Hsing HSIEH ,  Wen-Koi LAI ,  Keng-Hua KUO ,  KuoPei LU ,  Lester CHANG ,  Ze-Ming WU

IPC分类号： G06F30/398 ,  G03F1/70 ,  G03F1/36 ,  G06F30/20

摘要： A method of generating an IC layout diagram includes receiving a first gate resistance value of a gate region in an IC layout diagram, the first gate resistance value corresponding to a location of a gate via positioned within an active region and along a width of the gate region extending across the active region, determining a second gate resistance value based on the location and the width, using the first and second resistance values to determine that the IC layout diagram does not comply with a design specification, and based on the non-compliance with the design specification, modifying the IC layout diagram.

公开(公告)号：US20210351282A1

公开(公告)日：2021-11-11

申请号：US17379551

申请日：2021-07-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Yi PENG ,  Wen-Yuan CHEN ,  Wen-Hsing HSIEH ,  Yi-Ju HSU ,  Jon-Hsu HO ,  Song-Bor LEE ,  Bor-Zen TIEN

IPC分类号： H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/02

摘要： A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.