公开(公告)号：US20240322011A1

公开(公告)日：2024-09-26

申请号：US18737803

申请日：2024-06-07

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Cheng-Yi PENG ,  Wen-Yuan CHEN ,  Wen-Hsing HSIEH ,  Yi-Ju HSU ,  Jon-Hsu HO ,  Song-Bor LEE ,  Bor-Zen TIEN

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L21/8234 ,  H01L27/088

CPC分类号： H01L29/66545 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886

摘要： A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.

公开(公告)号：US20220352319A1

公开(公告)日：2022-11-03

申请号：US17857104

申请日：2022-07-04

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/66

摘要： Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

公开(公告)号：US20240038866A1

公开(公告)日：2024-02-01

申请号：US17875975

申请日：2022-07-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Ching WANG ,  Chung-I YANG ,  Wei-Yang LEE ,  Wen-Hsing HSIEH

IPC分类号： H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/42392 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/41775 ,  H01L29/66553 ,  H01L29/66545 ,  H01L29/6656

摘要： A method for forming a semiconductor device structure is provided. The method includes providing a substrate. The method includes forming a nanostructure stack over the substrate. The method includes forming a gate stack over the nanostructure stack and the substrate. The method includes removing the first nanostructure forming a first gap between the substrate and the second nanostructure. The method includes forming a first spacer layer in the first gap and a gate spacer over a sidewall of the gate stack. The method includes partially removing the nanostructure stack, which is not covered by the gate stack and the gate spacer, to form a first trench in the nanostructure stack. The method includes forming a source/drain structure in the first trench and over the first spacer layer.

公开(公告)号：US20230246026A1

公开(公告)日：2023-08-03

申请号：US18132924

申请日：2023-04-10

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Chun-Chung SU ,  Chung-Wei WU ,  Jon-Hsu HO ,  Kuan-Lun CHENG ,  Wen-Hsing HSIEH ,  Wen-Yuan CHEN ,  Zhi-Qiang WU

IPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/06

CPC分类号： H01L27/088 ,  H01L21/764 ,  H01L29/0649 ,  H01L29/0847

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall. The structure also includes a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure further includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

公开(公告)号：US20230207629A1

公开(公告)日：2023-06-29

申请号：US18118010

申请日：2023-03-06

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Kuan-Lun CHENG ,  Wen-Hsing HSIEH

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L23/528 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L29/0847 ,  H01L29/0653 ,  H01L29/41791 ,  H01L23/528 ,  H01L21/76846 ,  H01L23/53209 ,  H01L29/4236

摘要： A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure includes a substrate having a front side and a back side opposing the front side, a gate stack disposed on the front side of the substrate, and a first source/drain feature and a second source/drain feature disposed in opposing sides of the gate stack. Each first source/drain feature and second source/drain feature comprises a first side and a second side, and a portion of the back side of the substrate is exposed to an air gap.

公开(公告)号：US20230020933A1

公开(公告)日：2023-01-19

申请号：US17377796

申请日：2021-07-16

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wen-Yuan CHEN ,  Chun-Chung SU ,  Jon-Hsu HO ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG ,  Chung-Wei WU ,  Zhiqiang WU

IPC分类号： H01L27/088 ,  H01L21/764

摘要： A semiconductor device structure includes a dielectric layer, a first source/drain feature in contact with the dielectric layer, wherein the first source/drain feature comprises a first sidewall, and a second source/drain feature in contact with the dielectric layer and adjacent to the first source/drain feature, wherein the second source/drain feature comprises a second sidewall. The structure also includes an insulating layer disposed over the dielectric layer and between the first sidewall and the second sidewall, wherein the insulating layer comprises a first surface facing the first sidewall, a second surface facing the second sidewall, a third surface connecting the first surface and the second surface, and a fourth surface opposite the third surface. The structure includes a sealing material disposed between the first sidewall and the first surface, wherein the sealing material, the first sidewall, the first surface, and the dielectric layer are exposed to an air gap.

公开(公告)号：US20220359657A1

公开(公告)日：2022-11-10

申请号：US17308258

申请日：2021-05-05

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Kuan-Lun CHENG ,  Wen-Hsing HSIEH

IPC分类号： H01L29/08 ,  H01L29/06 ,  H01L29/417 ,  H01L23/532 ,  H01L23/528 ,  H01L21/768

摘要： A semiconductor device structure, along with methods of forming such, are described. In one embodiment, a semiconductor device structure is provided. The semiconductor device structure a first source/drain region, a second source/drain region, and a gate stack disposed between the first source/drain region and the second source/drain region. The semiconductor device structure also includes a conductive feature disposed below the first source/drain region. The semiconductor device structure also includes a power rail disposed below and in contact with the conductive feature. semiconductor device structure also includes a dielectric layer enclosing the conductive feature, wherein an air gap is formed between the dielectric layer and the conductive feature.

公开(公告)号：US20190340328A1

公开(公告)日：2019-11-07

申请号：US16389679

申请日：2019-04-19

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

发明人： Ke-Ying SU ,  Jon-Hsu HO ,  Ke-Wei SU ,  Liang-Yi CHEN ,  Wen-Hsing HSIEH ,  Wen-Koi LAI ,  Keng-Hua KUO ,  KuoPei LU ,  Lester CHANG ,  Ze-Ming WU

IPC分类号： G06F17/50 ,  G03F1/36 ,  G03F1/70

摘要： A method of generating a netlist of an IC device includes extracting dimensions of a gate region of the IC device, the dimensions including a width of the gate region, the width extending at least from a first edge of an active region to a second edge of the active region, and a distance from a first end of the width to a gate via positioned along the width. A first gate resistance value corresponding to the gate region is received, a second gate resistance value is determined based on the distance and the width, and the netlist is updated based on the first and second gate resistance values.

公开(公告)号：US20240250125A1

公开(公告)日：2024-07-25

申请号：US18436052

申请日：2024-02-08

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Chih-Ching WANG ,  Wei-Yang LEE ,  Ming-Chang WEN ,  Jo-Tzu HUNG ,  Wen-Hsing HSIEH ,  Kuan-Lun CHENG

IPC分类号： H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/1033 ,  H01L29/4238 ,  H01L29/66818 ,  H01L29/785 ,  H01L2029/7858

摘要： Embodiments of the present disclosure provide a semiconductor device structure including a first channel layer formed of a first material, wherein the first channel layer has a first width, a second channel layer formed of a second material different from the first material, wherein the second channel layer has a second width less than the first width, and the second channel layer is in contact with a first surface of the first channel layer. The structure also includes a third channel layer formed of the second material, wherein the third channel layer has a third width less than the second width, and the third channel layer is in contact with a second surface of the first channel layer. The structure also includes a gate dielectric layer conformally disposed on the first channel layer, the second channel layer, and the third channel layer, and a gate electrode layer disposed on the gate dielectric layer.

公开(公告)号：US20230307522A1

公开(公告)日：2023-09-28

申请号：US18130296

申请日：2023-04-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Cheng-Yi PENG ,  Wen-Yuan CHEN ,  Wen-Hsing HSIEH ,  Yi-Ju HSU ,  Jon-Hsu HO ,  Song-Bor LEE ,  Bor-Zen TIEN

IPC分类号： H01L29/66 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/66545 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02203 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L27/0886

摘要： A method of manufacturing a semiconductor device, a plurality of fin structures are formed over a semiconductor substrate. The fin structures extend along a first direction and are arranged in a second direction crossing the first direction. A plurality of sacrificial gate structures extending in the second direction are formed over the fin structures. An interlayer dielectric layer is formed over the plurality of fin structures between adjacent sacrificial gate structures. The sacrificial gate structures are cut into a plurality of pieces of sacrificial gate structures by forming gate end spaces along the second direction. Gate separation plugs are formed by filling the gate end spaces with two or more dielectric materials. The two or more dielectric materials includes a first layer and a second layer formed on the first layer, and a dielectric constant of the second layer is smaller than a dielectric constant of the first layer.