MULTILAYER CERAMIC CAPACITOR
    11.
    发明申请

    公开(公告)号:US20170365409A1

    公开(公告)日:2017-12-21

    申请号:US15457026

    申请日:2017-03-13

    CPC classification number: H01G4/30 H01G4/0085 H01G4/012 H01G4/1227 H01G4/2325

    Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the external electrodes; a dielectric layer stacked on the first internal electrode and containing the base metal and a ceramic material mainly composed of barium titanate; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the external electrodes, wherein a concentration of the base metal in each of five regions, which are equally divided regions between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, is within ±20% of an average of the concentrations of the base metal in the five regions, and an atomic concentration ratio of Mg to Ti is 0 or greater and less than 0.002 in the dielectric layer.

    MULTILAYER CERAMIC CAPACITOR
    12.
    发明申请
    MULTILAYER CERAMIC CAPACITOR 审中-公开
    多层陶瓷电容器

    公开(公告)号:US20160035492A1

    公开(公告)日:2016-02-04

    申请号:US14805426

    申请日:2015-07-21

    Abstract: In some embodiments, a multilayer ceramic capacitor 10 has 23 unit capacitors UC1 to UC23, where these 23 unit capacitors UC1 to UC23 constitute: a first low-capacitance area LA1 constituted by three unit capacitors UC1 to UC3; a high-capacitance area HA constituted by 17 unit capacitors UC4 to UC20 whose unit capacitance is greater than that of the three unit capacitors UC1 to UC3; a second low-capacitance area LA2 constituted by three unit capacitors UC21 to UC23 whose unit capacitance is smaller than that of the 17 unit capacitors UC4 to UC20; a first variable-capacitance part which is present between the first low-capacitance area LA1 and high-capacitance area HA, and which includes the two adjacent unit capacitors UC3, UC4; and a second variable-capacitance part which is present between the high-capacitance area HA and second low-capacitance area LA2, and which includes the two adjacent unit capacitors UC20, UC21.

    Abstract translation: 在一些实施例中,多层陶瓷电容器10具有23个单位电容器UC1至UC23,其中这23个单位电容器UC1至UC23构成:由三个单位电容器UC1至UC3构成的第一低电容区域LA1; 由单位电容大于三个单位电容器UC1〜UC3的单位电容的17个单位电容器UC4〜UC20构成的高电容区域HA; 由单位电容小于17单位电容器UC4〜UC20的单位电容器UC21〜UC23构成的​​第二低电容区域LA2; 存在于第一低电容区域LA1和高电容区域HA之间的第一可变电容部分,并且包括两个相邻的单位电容器UC3,UC4; 以及存在于高电容区域HA和第二低电容区域LA2之间的第二可变电容部分,并且包括两个相邻的单位电容器UC20,UC21。

    CERAMIC ELECTRONIC DEVICE AND MANUFACTURING METHOD OF CERAMIC ELECTRONIC DEVICE

    公开(公告)号:US20220285094A1

    公开(公告)日:2022-09-08

    申请号:US17584994

    申请日:2022-01-26

    Abstract: A ceramic electronic device includes a multilayer structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. A main component of the plurality of dielectric layers is a ceramic having a perovskite structure of which an A site includes at least Ba and of which an AB ratio is 0.980 or less. The plurality of internal electrode layers include a co-material. A total amount of Ti, Zr and Hf is 90 mol % or more in metal elements included in the co-material and an amount of Ba is 10 mol % or less in the metal elements.

    MULTILAYER CERAMIC CAPACITOR AND DIELECTRIC MATERIAL

    公开(公告)号:US20210383973A1

    公开(公告)日:2021-12-09

    申请号:US17317608

    申请日:2021-05-11

    Abstract: A multilayer ceramic capacitor includes a multilayer structure having a substantially rectangular parallelepiped shape and including dielectric layers and internal electrode layers that are alternately stacked, the dielectric layers being mainly composed of BaTiO3, the internal electrode layers being alternately exposed to two edge faces of the multilayer chip opposite to each other. A Zr/Ti ratio is 0.02 or more and 0.10 or less in a capacity section. A Ba/Ti ratio is more than 0.900 and less than 1.010 in the capacity section. A Eu/Ti ratio is 0.005 or more and 0.05 or less in the capacity section. A Mn/Ti ratio is 0.0005 or more and 0.05 or less in the capacity section. A total amount of a rare earth element or rare earth elements is less than the amount of Eu.

    MULTILAYER CERAMIC CAPACITOR AND MANUFACTURING METHOD OF THE SAME

    公开(公告)号:US20210151254A1

    公开(公告)日:2021-05-20

    申请号:US17161423

    申请日:2021-01-28

    Abstract: A multilayer ceramic capacitor includes: a multilayer structure having a parallelepiped shape in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked and are alternately exposed to two edge faces of the multilayer structure, a main component of the plurality of dielectric layers being a ceramic; and a first cover layer and a second cover layer that sandwich the multilayer structure in a stacking direction of the multilayer structure, a main component of the first cover layer and the second cover layer being the same as that of the dielectric layers, wherein the first cover layer includes a first region spaced from the multilayer structure by at least 50 μm, is thicker than the second cover layer, and has a thickness more than 50 μm.

    CERAMIC ELECTRONIC DEVICE AND MANUFACTURING METHOD OF THE SAME

    公开(公告)号:US20210118617A1

    公开(公告)日:2021-04-22

    申请号:US17034915

    申请日:2020-09-28

    Inventor: Koichiro MORITA

    Abstract: A multilayer ceramic capacitor includes: a multilayer structure in which each of a plurality of dielectric layers and each of a plurality of internal electrode layers are alternately stacked. A ceramic protection section includes a cover layer and a side margin. A main component ceramic of the ceramic protection section is a ceramic material having a perovskite structure expressed as a general formula ABO3. An A site of the perovskite structure includes at least Ba. A B site of the perovskite structure includes at least Ti and Zr. A Zr/Ti ratio which is a molar ratio of Zr and Ti is 0.010 or more and 0.25 or less. An A/B ratio which is a molar ratio of the A site and the B site is 0.990 or less.

    MULTILAYER CERAMIC CAPACITOR
    19.
    发明申请

    公开(公告)号:US20170365406A1

    公开(公告)日:2017-12-21

    申请号:US15456368

    申请日:2017-03-10

    CPC classification number: H01G4/30 H01G4/012 H01G4/1227 H01G4/2325

    Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode that is coupled to one of the pair of external electrodes; a dielectric layer that is stacked on the first internal electrode and contains BaTiO3 and Ni; and a second internal electrode that is stacked on the dielectric layer, contains Ni, and is coupled to another one of the pair of external electrodes, wherein Ni concentrations obtained by analyzing five regions with a transmission electron microscope are within a range from 0.015 to 0.045, the five regions being obtained by dividing a region from a location 50 nm away from the first internal electrode of the dielectric layer to a location 50 nm away from the second internal electrode of the dielectric layer in a stacking direction between the first internal electrode and the second internal electrode equally into five.

    MULTI-LAYER CERAMIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME
    20.
    发明申请
    MULTI-LAYER CERAMIC CAPACITOR AND METHOD OF MANUFACTURING THE SAME 有权
    多层陶瓷电容器及其制造方法

    公开(公告)号:US20140285950A1

    公开(公告)日:2014-09-25

    申请号:US14033324

    申请日:2013-09-20

    CPC classification number: H01G4/12 H01G4/012 H01G4/1227 H01G4/20 H01G4/30

    Abstract: A multi-layer ceramic capacitor is constituted by ceramic dielectric layers alternately laminated with conductive layers, wherein the ceramic dielectric layers are sintered in such a way that core-shell grains having a core-shell structure are mixed with uniform solid-solution grains resulting from uniform progression of the solid solution process. Such multi-layer ceramic capacitor is characterized in that the area ratio of the core-shell grains to all sintered grains constituting the ceramic dielectric layer is 5 to 15% and that the average grain size of all sintered grains including the core-shell grains and uniform solid-solution grains is 0.3 to 0.5 μm.

    Abstract translation: 多层陶瓷电容器由交替层叠有导电层的陶瓷电介质层构成,其中陶瓷电介质层被烧结,使得具有核 - 壳结构的核 - 壳颗粒与均匀的固溶颗粒混合,由 固溶过程的均匀进展。 这种多层陶瓷电容器的特征在于,核 - 壳晶粒与构成陶瓷电介质层的所有烧结晶粒的面积比为5〜15%,所有烧结晶粒的平均粒径包括核 - 壳粒和 均匀的固溶颗粒为0.3-0.5μm。

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