MULTILAYER CERAMIC ELECTRONIC DEVICE AND DIELECTRIC MATERIAL

    公开(公告)号:US20240242885A1

    公开(公告)日:2024-07-18

    申请号:US18397341

    申请日:2023-12-27

    Inventor: Koichiro MORITA

    Abstract: A multilayer ceramic electronic device includes internal electrodes, dielectric layers each of which includes a main component, a first subcomponent, a second subcomponent, and a third sub component. The main component includes titanium and includes at least one of barium or calcium. A molar ratio of a sum of barium and calcium to titanium is 1.045 or more and 1.100 or less. The first sub component includes 3 mol or more and 6 mol or less of a rare earth element, with respect to 100 mol of titanium in the dielectric layers. The second sub component includes 3 mol or more and 7 mol or less of manganese, with respect to 100 mol of titanium in the dielectric layers. The third sub component includes 0.6 weight % or more and 2.4 weight % or less of borosilicate glass with respect to each of the plurality of dielectric layers.

    MULTILAYER CERAMIC CAPACITOR
    4.
    发明申请

    公开(公告)号:US20170365412A1

    公开(公告)日:2017-12-21

    申请号:US15457337

    申请日:2017-03-13

    Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the external electrodes; a dielectric layer stacked on the first internal electrode and containing a ceramic material and the base metal; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the external electrodes, wherein a concentration of the base metal in each of five regions, which are equally divided regions of a region between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, is within ±20% of an average of the concentrations of the base metal in the five regions, and an average grain size in the dielectric layer is 200 nm or less.

    MULTILAYER CERAMIC CAPACITOR
    5.
    发明申请

    公开(公告)号:US20170365411A1

    公开(公告)日:2017-12-21

    申请号:US15457171

    申请日:2017-03-13

    CPC classification number: H01G4/30 H01G4/0085 H01G4/012 H01G4/1218 H01G4/1227

    Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the external electrodes; a dielectric layer stacked on the first internal electrode and containing a ceramic material and the base metal; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the external electrodes, wherein a concentration of the base metal in each of five regions, which are equally divided regions of a region between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, is within ±20% of an average of the concentrations of the base metal in the five regions, and the dielectric layer has a thickness of 0.6 μm or less.

    MULTILAYER CERAMIC CAPACITOR
    6.
    发明申请

    公开(公告)号:US20170365410A1

    公开(公告)日:2017-12-21

    申请号:US15457060

    申请日:2017-03-13

    CPC classification number: H01G4/30 H01G4/0085 H01G4/012 H01G4/1227 H01G4/2325

    Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode containing a base metal and coupled to one of the external electrodes; a dielectric layer stacked on the first internal electrode and containing a ceramic material and the base metal; and a second internal electrode stacked on the dielectric layer, containing the base metal, and coupled to another one of the pair external electrodes, a concentration of the base metal in each of five regions, which are equally divided regions of a region between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, being within ±20% of an average of the concentrations of the base metal in the five regions, an average grain number in the dielectric layer being three or less in the stacking direction between the first and second internal electrodes.

    MULTILAYER CERAMIC CAPACITOR
    7.
    发明申请

    公开(公告)号:US20170365405A1

    公开(公告)日:2017-12-21

    申请号:US15456339

    申请日:2017-03-10

    CPC classification number: H01G4/30 H01G4/012 H01G4/1227 H01G4/2325

    Abstract: A multilayer ceramic capacitor includes: a pair of external electrodes; a first internal electrode that is coupled to one of the pair of external electrodes; a dielectric layer that is stacked on the first internal electrode and contains BaTiO3 and Ni; and a second internal electrode that is stacked on the dielectric layer, contains Ni, and is coupled to another one of the pair of external electrodes, wherein Ni is contained in five regions, which are equally divided region of a region between locations 50 nm away from the first and second internal electrodes in a stacking direction between the first and second internal electrodes, and a Ni concentration in at least one of end regions located closest to the first internal electrode and the second internal electrode among the five regions is greater than a Ni concentration in a central region of the five regions by 10% or more.

    MULTILAYER CERAMIC ELECTRONIC DEVICE AND MANUFACTURING METHOD OF THE SAME

    公开(公告)号:US20230223196A1

    公开(公告)日:2023-07-13

    申请号:US18079315

    申请日:2022-12-12

    Inventor: Koichiro MORITA

    CPC classification number: H01G4/2325 H01G4/30 H01G4/248 H01G4/1227

    Abstract: A multilayer ceramic electronic device includes a multilayer chip having a plurality of internal electrode layers that face each other and a plurality of dielectric layers, each of which is sandwiched by two of the plurality of internal electrode layers, one end of at least one of the plurality of internal electrode layers being exposed at a side face of the multilayer chip, a first external electrode that is provided on the side face of the multilayer chip, is in contact with at least one of the each end of the plurality of internal electrode layers, and includes ceramic grains, and a second external electrode that is provided on the first external electrode, has a glass, and has a main component that is a same metal as that of the first external electrode.

    MULTILAYER CERAMIC ELECTRONIC DEVICE AND MANUFACTURING METHOD OF THE SAME

    公开(公告)号:US20230154681A1

    公开(公告)日:2023-05-18

    申请号:US17974438

    申请日:2022-10-26

    CPC classification number: H01G4/1245 H01G4/30

    Abstract: A multilayer ceramic electronic device includes a plurality of internal electrode layers that face each other; and a plurality of dielectric layers, each of which is sandwiched by each two of the plurality of internal electrode layers. A main component of the plurality of dielectric layers is barium titanate zirconate. In each of the plurality of dielectric layers, an amount of zirconium is 2 at % or more and 14 at % or less with respect a total amount of titanium and zirconium. Curie point of the plurality of dielectric layers is less than 85 degrees C. An average thickness of each of the plurality of dielectric layers is 1 μm or less.

    MULTILAYER CERAMIC CAPACITOR
    10.
    发明申请

    公开(公告)号:US20180240592A1

    公开(公告)日:2018-08-23

    申请号:US15892285

    申请日:2018-02-08

    Inventor: Koichiro MORITA

    Abstract: A multilayer ceramic capacitor includes: a multilayer structure in which each of ceramic dielectric layers and each of internal electrode layers are alternately stacked, the plurality of internal electrode layers being alternately exposed to a first edge face and a second edge face of the multilayer structure, wherein: a region in which a set of internal electrode layers exposed to the first edge face of the multilayer structure face with another set of internal electrode layers exposed to the second edge face of the multilayer structure is a capacity region; at least a part of the circumference region around the capacity region has a protective region of which an average grain diameter of a main component ceramic is larger than that of the capacity region and of which a concentration of a donor element in the main component ceramic is larger than that of the capacity region.

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