公开(公告)号：US09612962B2

公开(公告)日：2017-04-04

申请号：US14539526

申请日：2014-11-12

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Mullangi Venkata Ratna Reddy ,  Ajit Deepak Gupte ,  Arindam Basak

IPC: G06F13/28 ,  G06F12/08 ,  H04N19/433 ,  H04N19/51 ,  G06F12/0846

CPC classification number: G06F12/0848 ,  G06F13/28 ,  G06F2212/282 ,  H04N19/433 ,  H04N19/51

Abstract: In certain embodiments, methods and systems for multimedia data processing are provided. In an embodiment, a method for processing multimedia data includes defining one or more pixel block regions in a first cache so as to cache a plurality of reference pixel blocks corresponding to reference data. A reference pixel block from among the plurality of reference pixel blocks is assigned to a pixel block region from among the one or more pixel block regions based on a predetermined criterion. The reference pixel block is associated with a tag based on the pixel block region so as to facilitate a search of the reference data in order to process a plurality of pixel blocks associated with a multimedia frame of the multimedia data.

公开(公告)号：US20160050431A1

公开(公告)日：2016-02-18

申请号：US14925575

申请日：2015-10-28

Applicant: Texas Instruments Incorporated

Inventor： Ajit Deepak Gupte ,  Hetul Sanghvi ,  Herve Catan

IPC: H04N19/513 ,  H04N19/44 ,  H04N19/124 ,  H04N19/625 ,  H04N19/593 ,  H04N19/433

CPC classification number: H04N19/513 ,  H04N19/124 ,  H04N19/433 ,  H04N19/44 ,  H04N19/593 ,  H04N19/625

Abstract: A system and method for organizing pixel information in memory. A method according to an embodiment of the disclosure includes storing data representative of pixels of a scene in a growing window (“GW”) portion of a reference frame in an on-chip memory, storing data representative of pixels of the visual scene in a sliding window (“SW”) portion of the reference frame thereby forming a hybrid window, searching the memory to locate a portion of the stored data that corresponds with data representative of pixels in a current frame descriptive of the scene, performing motion estimation according to results of the search, generating a compressed version of the current frame according to results of the motion estimation, and storing the compressed version for later visual rendering. The system includes a processing unit and a video encoder. The processing unit includes an on-chip memory. The video encoder includes a motion estimation engine and a compression unit.

Abstract translation: 一种用于在存储器中组织像素信息的系统和方法。 根据本公开的实施例的方法包括将表示场景的像素的数据存储在片上存储器中的参考帧的增长窗口（“GW”）部分中，将代表视觉场景的像素的数据存储在 滑动窗口（“SW”），从而形成混合窗口，搜索存储器以定位与描述场景的当前帧中代表像素的数据相对应的存储数据的一部分，根据 搜索结果，根据运动估计的结果产生当前帧的压缩版本，并存储压缩版本供以后的视觉呈现。 该系统包括处理单元和视频编码器。 处理单元包括片上存储器。 视频编码器包括运动估计引擎和压缩单元。

公开(公告)号：US20240037700A1

公开(公告)日：2024-02-01

申请号：US18379249

申请日：2023-10-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mahesh M. Mehendale ,  Ajit Deepak Gupte

IPC: G06T3/40 ,  H04N19/523 ,  G06T7/238 ,  H04N19/43

CPC classification number: G06T3/4007 ,  H04N19/523 ,  G06T7/238 ,  H04N19/43 ,  G06T2207/10016 ,  G06T2207/20021

Abstract: The architecture shown can perform global search, local search and local sub pixel search in a parallel or in a pipelined mode. All operations are in a streaming mode without the requirement of external intermediate data storage.

公开(公告)号：US10423414B2

公开(公告)日：2019-09-24

申请号：US14539674

申请日：2014-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ajit Deepak Gupte ,  Mahesh Mehendale ,  Navin Acharya ,  Mel Alan Phipps

IPC: G06F9/30 ,  G06F9/48 ,  G06F9/38 ,  G06T1/20

Abstract: In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.

公开(公告)号：US20180234687A1

公开(公告)日：2018-08-16

申请号：US15954139

申请日：2018-04-16

Applicant: Texas Instruments Incorporated

Inventor： Ajit Deepak Gupte ,  Ranga Ramanujam Srinivasan

IPC: H04N19/186 ,  H04N19/147 ,  H04N19/107 ,  H04N19/176

CPC classification number: H04N19/186 ,  H04N19/107 ,  H04N19/147 ,  H04N19/176

Abstract: Several methods and systems for chroma residual data prediction for encoding blocks corresponding to video data are disclosed. In an embodiment, at least one coefficient correlating reconstructed luma residual samples and corresponding reconstructed chroma residual samples is computed for one or more encoded blocks of video data. Predicted chroma residual samples are generated for encoding a block of video data based on corresponding reconstructed luma residual samples and the at least one coefficient.

公开(公告)号：US20160132329A1

公开(公告)日：2016-05-12

申请号：US14539674

申请日：2014-11-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ajit Deepak Gupte ,  Mahesh Mehendale ,  Navin Acharya ,  Mel Alan Phipps

IPC: G06F9/30 ,  G06F9/48

Abstract: In an embodiment, a device including a processor, a plurality of hardware accelerator engines and a hardware scheduler is disclosed. The processor is configured to schedule an execution of a plurality of instruction threads, where each instruction thread includes a plurality of instructions associated with an execution sequence. The plurality of hardware accelerator engines performs the scheduled execution of the plurality of instruction threads. The hardware scheduler is configured to control the scheduled execution such that each hardware accelerator engine is configured to execute a corresponding instruction and the plurality of instructions are executed by the plurality of hardware accelerator engines in a sequential manner. The plurality of instruction threads are executed by plurality of hardware accelerator engines in a parallel manner based on the execution sequence and an availability status of each of the plurality of hardware accelerator engines.

Abstract translation: 在一个实施例中，公开了一种包括处理器，多个硬件加速器引擎和硬件调度器的设备。 处理器被配置为调度多个指令线程的执行，其中每个指令线程包括与执行序列相关联的多个指令。 多个硬件加速器引擎执行多个指令线程的调度执行。 硬件调度器被配置为控制调度的执行，使得每个硬件加速器引擎被配置为执行相应的指令，并且多个指令由多个硬件加速器引擎以顺序的方式执行。 基于执行顺序和多个硬件加速器引擎中的每一个的可用性状态，多个指令线程以并行方式由多个硬件加速器引擎执行。

公开(公告)号：US20130279587A1

公开(公告)日：2013-10-24

申请号：US13859994

申请日：2013-04-10

Applicant: Texas Instruments Incorporated

Inventor： Ajit Deepak Gupte ,  Mahesh M. Mehendale ,  Hetul Sanghvi ,  Ajit Venkat Rao

IPC: H04N7/34

CPC classification number: H04N19/00763 ,  H04N19/428 ,  H04N19/433 ,  H04N19/593 ,  H04N19/61

Abstract: A method, system and apparatus of lossy compression technique for video encoder bandwidth reduction using compression error data are disclosed. In one embodiment, a method includes storing an error data from a compression of an original reference data in an off-chip memory, accessing the error data during a motion compensation operation, and performing the motion compensation operation by applying the error data through an algorithm (e.g., determined by the method of storing the error data). The method may include generating a predicted frame in the motion compensation operation using a motion vector and an on-chip video data. In addition, the method may include determining the error data as a difference between a compressed reference data (e.g., is created by compressing the original reference data) and an original reference data (e.g., reconstructed from a prior predicted frame and a decompressed encoder data).