公开(公告)号：US20240027508A1

公开(公告)日：2024-01-25

申请号：US18128912

申请日：2023-03-30

Applicant: Texas Instruments Incorporated

Inventor： Aatish Chandak ,  Aravind Miriyala ,  Midhun Raveendran ,  Anand Hariraj Udupa ,  Raja Reddy Patukuri ,  Prabin Krishna Yadav

IPC: G01R31/00 ,  A61B5/053

CPC classification number: G01R31/002 ,  A61B5/053 ,  A61B2560/0223

Abstract: An example apparatus includes: calibration circuitry configured to determine a second current at a second terminal of a second impedance circuit based on a first parasitic capacitance, a first impedance value, a third impedance value, a first voltage, and a second voltage; determine a third voltage at a second terminal of a second impedance circuit based on the first parasitic capacitance, a second impedance value, the third impedance value, the second voltage, and the second current; and determine a second parasitic capacitance between the second terminal of the second impedance circuit and the second terminal of a fifth impedance circuit based on the second current, the third voltage, a third current at the second terminal of the fifth impedance circuit, and a fourth voltage at the second terminal of the fifth impedance circuit.

公开(公告)号：US20210003523A1

公开(公告)日：2021-01-07

申请号：US16852736

申请日：2020-04-20

Applicant: Texas Instruments Incorporated

Inventor： Aatish Chandak ,  Raja Reddy Patukuri ,  Aravind Miriyala ,  Sandeep Oswal

IPC: G01N27/02 ,  A61B5/053 ,  A61B5/00

Abstract: The disclosure provides a measurement circuit. The measurement circuit includes a control engine. An excitation source is coupled to the control engine. A first set of electrodes and a second set of electrodes are coupled to the excitation source and receive current from the excitation source. The control engine operates the excitation source in a first mode and a second mode. The control engine, in the first mode, measures a parasitic impedance associated with the first and the second set of electrodes, and the control engine, in the second mode, measures an impedance of the first and the second set of electrodes and of an external object.

公开(公告)号：US10677903B2

公开(公告)日：2020-06-09

申请号：US15367982

申请日：2016-12-02

Applicant: Texas Instruments Incorporated

Inventor： Ravikumar Pattipaka ,  Raja Sekhar Kanakamedala ,  Aravind Miriyala ,  Vajeed Nimran P A ,  Sandeep Kesrimal Oswal

IPC: G01S7/52 ,  A61B8/00 ,  A61B8/08

Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.

公开(公告)号：US10319362B2

公开(公告)日：2019-06-11

申请号：US15793537

申请日：2017-10-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Ravikumar Pattipaka ,  Raja Sekhar Kanakamedala ,  Aravind Miriyala ,  Sandeep Kesrimal Oswal

IPC: G10K11/34 ,  H03K17/687 ,  H03K19/003 ,  H03K3/356 ,  G10K11/04 ,  G06F1/3203 ,  H03K17/08 ,  G11C11/413 ,  H03K19/0185 ,  B06B1/02 ,  H03K17/56

Abstract: The disclosure provides a level shifter. The level shifter includes a first logic block that receives an input signal and generates a primary pulsed input. A first transistor is coupled to the first logic block and a first node. A gate terminal of the first transistor receives the primary pulsed input. A latch is coupled to the first node and a second node. A second logic block receives the input signal and generates a secondary pulsed input. A second transistor is coupled between the second logic block and the second node. A gate terminal of the second transistor receives the secondary pulsed input.