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1.发明公开公开(公告)号：US20240171144A1
公开(公告)日：2024-05-23
申请号：US17990682
申请日：2022-11-19
Applicant: Texas Instruments Incorporated
Inventor： Ravikumar Pattipaka , Prashuk Jain , Vajeed Nimran
IPC: H03F3/45
CPC classification number: H03F3/45928 , H03F3/45076 , H03F2200/231 , H03F2200/294
Abstract: A differential to single-ended summation circuit includes a first switch which includes a first terminal coupled to a first circuit input and includes a second terminal. The circuit includes a second switch which includes a first terminal coupled to a second circuit input and includes a second terminal. The circuit includes a holding capacitor which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the second terminal of the second switch. The circuit includes a third switch which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to a circuit output. The circuit includes a fourth switch including a first terminal coupled to the second terminal of the second switch and a second terminal coupled to a common potential.
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公开(公告)号：US20240243714A1
公开(公告)日：2024-07-18
申请号：US18193243
申请日：2023-03-30
Applicant: Texas Instruments Incorporated
Inventor： Ravikumar Pattipaka , Raja Sekhar , Sandeep Oswal
CPC classification number: H03F3/45475 , H03F1/3211 , H03G3/3042
Abstract: An ultrasonic transmitter including a linear amplifier, an output stage, a switch, and a current compensation circuit. The linear amplifier includes first and second amplifier stages. The output stage has an input coupled to output of the linear amplifier, and presents the transmitter output. The switch is coupled to the output of the linear amplifier. The current compensation circuit has an output coupled at the output of the first amplifier stage. Select circuitry is configured to couple the switch to a bias terminal when the switch is closed, and to couple one or more nodes of the switch to the control terminal of the current compensation circuit when the switch is open. The current compensation circuit generates a compensation current responsive to a sensed non-linear current conducted through the switch when open.
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公开(公告)号：US11740208B2
公开(公告)日：2023-08-29
申请号：US17350552
申请日：2021-06-17
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prashuk Jain , Ravikumar Pattipaka , Vajeed Nimran Parambil Abdul Raheem , Sandeep Kesrimal Oswal
CPC classification number: G01N29/2468 , G01N29/36 , G01S7/491 , G01S7/5208 , G01S7/52023 , G01S7/52095 , G06F7/582
Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
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公开(公告)号：US20240238841A1
公开(公告)日：2024-07-18
申请号：US18192863
申请日：2023-03-30
Applicant: Texas Instruments Incorporated
Inventor： Raja Sekhar , Ravikumar Pattipaka , Sandeep Oswal
CPC classification number: B06B1/0207 , B06B1/06 , H03F3/183 , A61B8/4488 , H03F2200/03
Abstract: An ultrasonic transceiver system including a transducer, a receiver coupled to the transducer, a transmitter having an output terminal coupled to the transducer, and a transmit/receive switch configured to isolate the receiver from the transmitter during transmission. The transmitter includes an amplifier and an output stage. The output stage includes a source follower transistor having a drain coupled to a supply terminal, a gate coupled to an output of the amplifier, and a source coupled to an output terminal, along with a power stage transistor having a source coupled to the supply terminal, a gate coupled to the drain of the source follower transistor, and a drain coupled to the output terminal. The output stage further includes a parallel source follower transistor having a drain coupled to the supply terminal, a gate coupled to the input terminal, and a source coupled to the output terminal.
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公开(公告)号：US11067544B2
公开(公告)日：2021-07-20
申请号：US16220001
申请日：2018-12-14
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Prashuk Jain , Ravikumar Pattipaka , Vajeed Nimran Parambil Abdul Raheem , Sandeep Kesrimal Oswal
Abstract: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
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Patent Agency Ranking
公开(公告)号：US20180122360A1
公开(公告)日：2018-05-03
申请号：US15793537
申请日：2017-10-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Ravikumar Pattipaka , Raja Sekhar Kanakamedala , Aravind Miriyala , Sandeep Kesrimal Oswal
IPC: G10K11/34 , H03K17/687 , H03K19/003 , H03K3/356 , G11C11/413 , G06F1/32 , H03K17/08 , H03K17/56 , G10K11/04
CPC classification number: G10K11/341 , B06B1/0207 , G06F1/3203 , G10K11/04 , G11C11/413 , H03K3/356113 , H03K17/08 , H03K17/56 , H03K17/687 , H03K17/6871 , H03K19/00361 , H03K19/018507 , H03K2217/0063
Abstract: The disclosure provides a level shifter. The level shifter includes a first logic block that receives an input signal and generates a primary pulsed input. A first transistor is coupled to the first logic block and a first node. A gate terminal of the first transistor receives the primary pulsed input. A latch is coupled to the first node and a second node. A second logic block receives the input signal and generates a secondary pulsed input. A second transistor is coupled between the second logic block and the second node. A gate terminal of the second transistor receives the secondary pulsed input.
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7.发明授权公开(公告)号：US11888509B2
公开(公告)日：2024-01-30
申请号：US16234672
申请日：2018-12-28
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Aravind Miriyala , Ravikumar Pattipaka , Raja Sekhar Kanakamedala , Sandeep Kesrimal Oswal
CPC classification number: H04B1/44 , B06B1/023 , H03K17/00 , H03K17/002 , H04B11/00 , A61B8/14 , A61B8/54 , B06B2201/76
Abstract: An ultrasound system includes a transmit-receive switch. The transmit-receive switch includes a combined transmit-receive and return-to-zero (RTZ) path. The combined transmit-receive and RTZ path includes a transistor with a first current terminal, a second current terminal, and a control terminal. The second current terminal of the transistor is coupled to a ground node via a first switch and is coupled to a receive node via a second switch. The ultrasound system also includes a receiver front-end circuit coupled to the receive node.
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公开(公告)号：US11662448B2
公开(公告)日：2023-05-30
申请号：US17487259
申请日：2021-09-28
Applicant: Texas Instruments Incorporated
Inventor： Ravikumar Pattipaka , Raja Sekhar Kanakamedala , Aravind Miriyala , Vajeed Nimran P A , Sandeep Kesrimal Oswal
CPC classification number: G01S7/52077 , A61B8/4483 , A61B8/5269
Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.
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公开(公告)号：US11163046B2
公开(公告)日：2021-11-02
申请号：US16859440
申请日：2020-04-27
Applicant: Texas Instruments Incorporated
Inventor： Ravikumar Pattipaka , Raja Sekhar Kanakamedala , Aravind Miriyala , Vajeed Nimran P A , Sandeep Kesrimal Oswal
Abstract: Methods and apparatus for reducing a transient glitch in ultrasound applications are disclosed. An example apparatus includes a transducer to (A) output a signal during a transmit phase and (B) receive a reflected signal corresponding to the signal during a receive phase; a receiver switch coupled to the transducer at a first node, the receiver switch to (A) open during the transmit phase and (B) close during the receive phase; and a clamp coupled to the transducer at the first node, the clamp to provide a high impedance during the transmit phase and the receive phase and provide a low impedance during a transient phase.
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公开(公告)号：US20250007484A1
公开(公告)日：2025-01-02
申请号：US18217325
申请日：2023-06-30
Applicant: Texas Instruments Incorporated
Inventor： Raja Sekhar , Prashuk Jain , Sandeep Oswal , Ravikumar Pattipaka
Abstract: Methods, apparatus, systems, and articles of manufacture are described corresponding to current limit circuitry with controlled current variation. An example circuit includes an amplifier having an input terminal and an output terminal; a capacitor having a first terminal and a second terminal, the first terminal of the capacitor coupled to the input terminal of the amplifier, the second terminal of the capacitor coupled to the output terminal of the amplifier; and diode circuitry having a first terminal and a second terminal, the first terminal of the diode circuitry coupled to the first terminal of the capacitor and the input terminal of the amplifier, the second terminal of the diode circuitry coupled to the second terminal of the capacitor and the output terminal of the amplifier.
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