Differential To Single-Ended Summation Circuit With Improved Common-Mode Rejection Ratio

    公开(公告)号:US20240171144A1

    公开(公告)日:2024-05-23

    申请号:US17990682

    申请日:2022-11-19

    IPC分类号: H03F3/45

    摘要: A differential to single-ended summation circuit includes a first switch which includes a first terminal coupled to a first circuit input and includes a second terminal. The circuit includes a second switch which includes a first terminal coupled to a second circuit input and includes a second terminal. The circuit includes a holding capacitor which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to the second terminal of the second switch. The circuit includes a third switch which includes a first terminal coupled to the second terminal of the first switch and a second terminal coupled to a circuit output. The circuit includes a fourth switch including a first terminal coupled to the second terminal of the second switch and a second terminal coupled to a common potential.

    Linearity Correction in High Voltage Transmit Switches

    公开(公告)号:US20240243714A1

    公开(公告)日:2024-07-18

    申请号:US18193243

    申请日:2023-03-30

    IPC分类号: H03F3/45 H03F1/32 H03G3/30

    摘要: An ultrasonic transmitter including a linear amplifier, an output stage, a switch, and a current compensation circuit. The linear amplifier includes first and second amplifier stages. The output stage has an input coupled to output of the linear amplifier, and presents the transmitter output. The switch is coupled to the output of the linear amplifier. The current compensation circuit has an output coupled at the output of the first amplifier stage. Select circuitry is configured to couple the switch to a bias terminal when the switch is closed, and to couple one or more nodes of the switch to the control terminal of the current compensation circuit when the switch is open. The current compensation circuit generates a compensation current responsive to a sensed non-linear current conducted through the switch when open.

    Output Stage for High-Voltage Linear Transmitters

    公开(公告)号:US20240238841A1

    公开(公告)日:2024-07-18

    申请号:US18192863

    申请日:2023-03-30

    IPC分类号: B06B1/02 B06B1/06 H03F3/183

    摘要: An ultrasonic transceiver system including a transducer, a receiver coupled to the transducer, a transmitter having an output terminal coupled to the transducer, and a transmit/receive switch configured to isolate the receiver from the transmitter during transmission. The transmitter includes an amplifier and an output stage. The output stage includes a source follower transistor having a drain coupled to a supply terminal, a gate coupled to an output of the amplifier, and a source coupled to an output terminal, along with a power stage transistor having a source coupled to the supply terminal, a gate coupled to the drain of the source follower transistor, and a drain coupled to the output terminal. The output stage further includes a parallel source follower transistor having a drain coupled to the supply terminal, a gate coupled to the input terminal, and a source coupled to the output terminal.

    Switched capacitor delay line
    5.
    发明授权

    公开(公告)号:US11067544B2

    公开(公告)日:2021-07-20

    申请号:US16220001

    申请日:2018-12-14

    摘要: A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.