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公开(公告)号：US11740208B2
公开(公告)日：2023-08-29
申请号：US17350552
申请日：2021-06-17
发明人： Prashuk Jain , Ravikumar Pattipaka , Vajeed Nimran Parambil Abdul Raheem , Sandeep Kesrimal Oswal
CPC分类号： G01N29/2468 , G01N29/36 , G01S7/491 , G01S7/5208 , G01S7/52023 , G01S7/52095 , G06F7/582
摘要： A delay line control circuit includes a pseudo-random number generator and a random phase generator circuit coupled to the pseudo-random number generator. The pseudo-random number generator is configured to produce a predetermined sequence of pseudo-random values. The random phase generator circuit is configured to randomize an access sequence for capacitors of a delay line. The random phase generator circuit includes a sequence register, an adder, and gating circuitry. The sequence register is configured to a store a value identifying one of the capacitors to be accessed. The adder is coupled to the sequence register, and is configured to increment the value stored in sequence register. The gating circuitry is coupled to the pseudo-random number generator and the adder. The gating circuitry is configured to pass one of the pseudo-random values to the adder for addition to the value stored in the sequence register.
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公开(公告)号：US10739433B2
公开(公告)日：2020-08-11
申请号：US15465484
申请日：2017-03-21
发明人： Anand Hariraj Udupa , Hussam Ahmed , Jagannathan Venkataraman , Sandeep Kesrimal Oswal , Prabin Krishna Yadav , Anand Reghunathan , Kiran Rajmohan
摘要： A system may comprise: an excitation current source; a first electrode coupled to the excitation current source; and a second electrode coupled to the excitation current source. The first and second electrodes may be configured to pass an excitation current from the excitation current source through a human body. First and second calibration resistors may be coupled to and positioned between the excitation current source and the first electrode. Third and fourth calibration resistors may be coupled to and positioned between the excitation current source and the second electrode. The system may also comprise a sensor configured to measure voltages across each of the first, second, third, and fourth calibration resistors.
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公开(公告)号：US20240283413A1
公开(公告)日：2024-08-22
申请号：US18625276
申请日：2024-04-03
发明人： Sravana Kumar Goli , Nagesh Surendranath , Srinivas Bangalore Seshadri , Sandeep Kesrimal Oswal
摘要： In described examples, a circuit includes an integrator. The integrator generates a first signal responsive to an input signal. A trigger circuit is coupled to the integrator and receives the first signal. A charge dump circuit is coupled to the integrator and the trigger circuit. The trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.
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公开(公告)号：US11979116B2
公开(公告)日：2024-05-07
申请号：US17137685
申请日：2020-12-30
发明人： Sravana Kumar Goli , Nagesh Surendranath , Srinivas Bangalore Seshadri , Sandeep Kesrimal Oswal
摘要： In described examples, a circuit includes an integrator. The integrator generates a first signal responsive to an input signal. A trigger circuit is coupled to the integrator and receives the first signal. A charge dump circuit is coupled to the integrator and the trigger circuit. The trigger circuit modifies configuration of the charge dump circuit and the integrator when the first signal is greater than a first threshold.
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公开(公告)号：US11476857B2
公开(公告)日：2022-10-18
申请号：US17072225
申请日：2020-10-16
摘要： Analog gain correction circuitry and analog switching clock edge timing correction circuitry can provide coarse correction of interleaving errors in radio-frequency digital-to-analog converters (RF DACs), such as may be used in 5G wireless base stations. The analog correction can be supplemented by digital circuitry configured to “pre-cancel” an interleaving image by adding to a digital DAC input signal a signal equal and opposite to an interleaving image created by the interleaving DAC, such that the interleaving image is effectively mitigated. Error correction control parameters can be periodically adjusted for changes in temperature by a controller coupled to an on-chip temperature sensor. A model useful for understanding the sources of error in interleaving DACs is also described.
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公开(公告)号：US10951226B2
公开(公告)日：2021-03-16
申请号：US16555160
申请日：2019-08-29
摘要： A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.
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公开(公告)号：US10581451B2
公开(公告)日：2020-03-03
申请号：US15950690
申请日：2018-04-11
发明人： Jagannathan Venkataraman , Prabu Sankar Thirugnanam , Raja Reddy Patukuri , Sandeep Kesrimal Oswal
IPC分类号： H03M3/00
摘要： The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.
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公开(公告)号：US10439631B1
公开(公告)日：2019-10-08
申请号：US16233207
申请日：2018-12-27
摘要： A digital-to-analog converter system has digital-to-analog converters, a common output, and a digital controller for transmitting first codes to one of the converters at a radio-frequency digital rate, and for transmitting second codes to another one of the converters at the same rate. The digital controller includes a timing system for operating each converter at the digital rate in a return-to-zero configuration, such that a signal from the first converter is transmitted to the common output while the second converter is reset, and vice versa. The digital-to-analog converter system can generate a radio-frequency analog signal having signals in first and second Nyquist zones simultaneously.
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公开(公告)号：US20180214084A1
公开(公告)日：2018-08-02
申请号：US15936029
申请日：2018-03-26
CPC分类号： A61B5/6898 , A61B5/053 , A61B5/0535 , A61B5/0537 , A61B5/7221 , A61B2560/0468
摘要： The disclosure provides a circuit for impedance measurement. The circuit includes an excitation source coupled between a first set of input switches. An impedance network is coupled between the first set of input switches and a first set of output switches. The impedance network includes a body impedance and a plurality of electrode impedances. A sense circuit is coupled to the first set of output switches. The sense circuit measures the body impedance and at least one electrode impedance of the plurality of electrode impedances.
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公开(公告)号：US20150260571A1
公开(公告)日：2015-09-17
申请号：US14644308
申请日：2015-03-11
发明人： Jagannathan Venkataraman , Prabu Sankar Thirugnanam , Raja Reddy Patukuri , Sandeep Kesrimal Oswal
IPC分类号： G01J1/44 , H03M3/00 , H01L27/144
摘要： The disclosure provides a receiver with high dynamic range. The receiver includes a photodiode that generates a current signal. A coupling capacitor is coupled to the photodiode, and generates a modulation signal in response to the current signal received from the photodiode. A sigma delta analog to digital converter (ADC) is coupled to the coupling capacitor, and generates a digital data in response to the modulation signal. A digital mixer is coupled to the sigma delta ADC, and generates an in-phase component and a quadrature component corresponding to the digital data. A processor is coupled to the digital mixer, and processes the in-phase component and the quadrature component corresponding to the digital data.
摘要翻译： 本公开提供了具有高动态范围的接收机。 接收器包括产生电流信号的光电二极管。 耦合电容器耦合到光电二极管，并且响应于从光电二极管接收的电流信号而产生调制信号。 Σ-Δ模数转换器（ADC）耦合到耦合电容器，并且响应于调制信号产生数字数据。 数字混频器耦合到Σ-ΔADC，并产生对应于数字数据的同相分量和正交分量。 处理器耦合到数字混频器，并处理与数字数据相对应的同相分量和正交分量。
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