公开(公告)号：US20160094203A1

公开(公告)日：2016-03-31

申请号：US14498048

申请日：2014-09-26

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/012 ,  H03K3/3562

CPC classification number: H03K3/012 ,  H03K3/35606 ,  H03K3/35625

Abstract: A flip-flop is disclosed that utilizes low area. The flip-flop includes a tri-state inverter that receive a flip-flop input, a clock input and an inverted clock input. A master latch receives an output of the tri-state inverter. The master latch includes a common inverter. A slave latch is coupled to the master latch. The common inverter is shared between the master latch and the slave latch. An output inverter is coupled to the common inverter and generates a flip-flop output.

Abstract translation: 公开了一种使用低面积的触发器。 触发器包括三态反相器，其接收触发器输入，时钟输入和反相时钟输入。 主锁存器接收三态反相器的输出。 主锁存器包括一个公共的逆变器。 从锁存器耦合到主锁存器。 公共逆变器在主锁存器和从锁存器之间共享。 输出反相器耦合到公共反相器并产生触发器输出。

公开(公告)号：US20160092170A1

公开(公告)日：2016-03-31

申请号：US14496767

申请日：2014-09-25

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: G06F7/50 ,  H03K19/00 ,  H03K19/20

CPC classification number: G06F7/50 ,  G06F7/501 ,  H03K19/0013 ,  H03K19/20

Abstract: A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum.

Abstract translation: 公开了一种利用低面积的全加器。 全加器包括一个异或逻辑电路。 异或逻辑电路接收第一输入和第二输入。 第一反相器接收异或逻辑电路的输出并产生异或输出。 进位发生电路接收异或逻辑电路的输出，异或输出和第三输入。 进位发生电路产生反转进位。 第二反相器耦合到进位发生电路，并产生接收反向进位的进位。 和产生电路接收异或逻辑电路的输出，异或输出和第三输入。 和产生电路产生一个反相和。 第三反相器耦合到和产生电路，并在接收到反相和时产生和。

公开(公告)号：US12211850B2

公开(公告)日：2025-01-28

申请号：US17514580

申请日：2021-10-29

Applicant: Texas Instruments Incorporated

Inventor： Rakesh Dimri ,  Badarish Mohan Subbannavar ,  Somasekar J

IPC: H01L27/118

Abstract: An IC includes first-third power rails over a semiconductor substrate. The first rail has a first polarity different from the second and third rails. The IC includes multiple first cells on the semiconductor substrate in first and second rows. The first row is separated from the second row by the first power rail. Each first cell includes a first height and a first structure having at least one transistor. For each first cell in the first row, the first structure is entirely between the first and second rails. Further, for each first cell in the second row, the first structure is between the first and third rails. The IC includes an extension cell arranged on the semiconductor substrate in the first row. The extension cell includes a second structure having at least one transistor. A portion of the second structure extends into the second row.

公开(公告)号：US11626879B2

公开(公告)日：2023-04-11

申请号：US17463115

申请日：2021-08-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Badarish Mohan Subbannavar ,  Rakesh Dimri ,  Somasekar J ,  Mohammad Asif Farooqui

IPC: H03K19/08

Abstract: An integrated circuit, and method of forming the same. The integrated circuit includes standard logic cells and a combined logic cell over a semiconductor substrate. Each standard logic cell includes a standard height, a width that is an integer multiple of a unit width, first and second power rails, and at least one transistor and interconnections configured to implement a logic function that produces a single logic output. The combined logic cell includes the standard height, a width that is an integer multiple of the unit width, the first and second power rails, and at least two transistors and interconnections configured to implement a first logic function and a second logic function. The first and second logic functions produce first and second logic outputs, respectively. The interconnections are configured to direct the first logic output and the second logic output to destinations outside the combined logic cell.

公开(公告)号：US20190319612A1

公开(公告)日：2019-10-17

申请号：US16452597

申请日：2019-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/3562 ,  H03K19/094 ,  H03K3/356 ,  H03K3/012 ,  H03K19/00

Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

公开(公告)号：US10382020B2

公开(公告)日：2019-08-13

申请号：US16042194

申请日：2018-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K3/3562 ,  H03K3/012 ,  H03K19/00 ,  H03K19/094 ,  H03K3/356

Abstract: At least some embodiments are directed to a flip-flop that comprises a tri-state inverter and a master latch coupled to the tri-state inverter and comprising a first transistor, a first inverter, and a first logic gate. The master latch receives a clock signal. The flop also comprises a slave latch coupled to the master latch and comprising a second transistor and a second inverter. The slave latch receives the clock signal. The flop further comprises an enablement logic coupled to the master latch and comprising multiple, additional logic gates. The tri-state inverter, the master and slave latches, and the enablement logic are configured so that when a flip-flop input signal D and a flip-flop output signal Q are identical and the clock signal is toggled, a state of the master latch and a state of the slave latch remain static.

公开(公告)号：US09246489B1

公开(公告)日：2016-01-26

申请号：US14499745

申请日：2014-09-29

Applicant: Texas Instruments Incorporated

Inventor： Suvam Nandi ,  Badarish Mohan Subbannavar

IPC: H03K19/00 ,  H03K19/0185 ,  H03K19/096 ,  H03K5/135 ,  H03K3/037

CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356173 ,  H03K5/135 ,  H03K19/0002 ,  H03K19/0016 ,  H03K19/01855 ,  H03K19/0966

Abstract: The disclosure provides an ICG (integrated clock gating) cell that utilizes a low area and a low power latch. The ICG cell includes a first logic gate that receives an enable signal and generates a latch input. A latch is coupled to the first logic gate and receives the latch input and a clock input. The latch includes a tri-state inverter and an inverting logic gate. The tri-state inverter is activated by a control signal generated by the inverting logic gate. A second logic gate receives the control signal and generates a gated clock.

Abstract translation: 本公开提供了利用低面积和低功率锁存器的ICG（集成时钟门控）单元。 ICG单元包括接收使能信号并产生锁存输入的第一逻辑门。 锁存器耦合到第一逻辑门并接收锁存器输入和时钟输入。 锁存器包括三态反相器和反相逻辑门。 三态反相器由反相逻辑门产生的控制信号激活。 第二逻辑门接收控制信号并产生门控时钟。