公开(公告)号：US20140129568A1

公开(公告)日：2014-05-08

申请号：US13922327

申请日：2013-06-20

Applicant: Texas Instruments Incorporated

Inventor： Hun-Seok Kim ,  Patrick Bosshart

IPC: G06F17/30

CPC classification number: G06F17/30949 ,  G06F12/0864 ,  G06F12/1018

Abstract: Hashing complexity is reduced by exploiting a hashing matrix structure that permits a corresponding hashing function to be implemented such that an output vector of bits is produced in response to an input vector of bits without combining every bit in the input vector with every bit in any row of the hashing matrix.

Abstract translation: 通过利用散列矩阵结构来减少哈希复杂度，该散列矩阵结构允许实现相应的散列函数，使得响应于输入向量的位而产生位的输出向量而不将输入向量中的每一位与每一行中的每个位组合 的哈希矩阵。

公开(公告)号：US10979353B2

公开(公告)日：2021-04-13

申请号：US15622936

申请日：2017-06-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/741 ,  H04L12/743

Abstract: A packet processing block. The block comprises an input for receiving data in a packet header vector, the vector comprising data values representing information for a packet. The block also comprises circuitry for performing packet match operations in response to at least a portion of the packet header vector and data stored in a match table, and circuitry for performing one or more actions in response to a match detected by the circuitry for performing packet match operations and according to information stored in an action table. Each of said match table and said action table comprise one or more memories selected from a pool of unit memories, wherein each memory in the pool of unit memories is configurable to operate as either a match memory or an action memory.

公开(公告)号：US10333847B2

公开(公告)日：2019-06-25

申请号：US15987041

申请日：2018-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/743 ,  G06F9/38

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

公开(公告)号：US10104004B2

公开(公告)日：2018-10-16

申请号：US14072989

申请日：2013-11-06

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/875 ,  H04L12/741 ,  H04L29/06 ,  H04L12/707

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

公开(公告)号：US20180270154A1

公开(公告)日：2018-09-20

申请号：US15987041

申请日：2018-05-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/743 ,  G06F9/38

CPC classification number: H04L45/7453 ,  G06F9/3853 ,  H04L45/7457

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

公开(公告)号：US10009276B2

公开(公告)日：2018-06-26

申请号：US14190734

申请日：2014-02-26

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/743 ,  G06F9/38

CPC classification number: H04L45/7453 ,  G06F9/3853 ,  H04L45/7457

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

公开(公告)号：US09258224B2

公开(公告)日：2016-02-09

申请号：US14190770

申请日：2014-02-26

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/28 ,  H04L12/56 ,  H04L12/741 ,  H04L12/935 ,  H04L12/743

CPC classification number: H04L45/745 ,  H04L45/74 ,  H04L45/7457 ,  H04L49/3063

Abstract: An embodiment of the invention includes a memory and apparatus for packet processing in a switching network. The memory includes a plurality of words where each word includes a plurality of bits. Each word in the plurality of words is addressed by separate and distinct read address. A logic circuit performs a logical “OR” function on all the bit in all the words addressed by the separate and distinct read addresses and outputs a result.

Abstract translation: 本发明的实施例包括用于交换网络中的分组处理的存储器和装置。 存储器包括多个单词，其中每个单词包括多个位。 多个单词中的每个单词通过单独和不同的读取地址来寻址。 逻辑电路对由单独和不同读取地址寻址的所有单词中的所有位执行逻辑“或”功能，并输出结果。

公开(公告)号：US20140241362A1

公开(公告)日：2014-08-28

申请号：US14193190

申请日：2014-02-28

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/761 ,  H04L29/06

CPC classification number: H04L69/22 ,  H04L45/00 ,  H04L45/74

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

Abstract translation: 一个数据包处理块。 该块具有用于在分组报头向量中接收数据的输入，该矢量包括表示分组的信息的数据和用于执行分组报头向量数据与至少一个匹配表之间的匹配操作的匹配单元。 各种实施例提供了在匹配表外部存储某些动作或下一个表位或表中的常数或通过从多个单元匹配表存储器形成匹配表的优点。

公开(公告)号：US10764200B2

公开(公告)日：2020-09-01

申请号：US16125838

申请日：2018-09-10

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/875 ,  H04L12/741 ,  H04L12/935 ,  H04L12/707 ,  H04L29/06 ,  H04L12/933 ,  H04L12/861

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

公开(公告)号：US20190007331A1

公开(公告)日：2019-01-03

申请号：US16125838

申请日：2018-09-10

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/875 ,  H04L12/741 ,  H04L12/707 ,  H04L29/06

CPC classification number: H04L47/56 ,  H04L45/24 ,  H04L45/745 ,  H04L49/1546 ,  H04L49/3009 ,  H04L49/3063 ,  H04L49/9094 ,  H04L69/22

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.