公开(公告)号：US20240345842A1

公开(公告)日：2024-10-17

申请号：US18754455

申请日：2024-06-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/383 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US20230297383A1

公开(公告)日：2023-09-21

申请号：US18321037

申请日：2023-05-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/383 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US11669330B2

公开(公告)日：2023-06-06

申请号：US17306350

申请日：2021-05-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/383 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/30043

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US20180275878A1

公开(公告)日：2018-09-27

申请号：US15991653

申请日：2018-05-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06F3/06 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F3/0604 ,  G06F3/0647 ,  G06F3/0673 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/383

Abstract: This disclosure is directed to the problem of paralleling random read access within a reasonably sized block of data for a vector SIMD processor. The invention sets up plural parallel look up tables, moves data from main memory to each plural parallel look up table and then employs a look up table read instruction to simultaneously move data from each parallel look up table to a corresponding part a vector destination register. This enables data processing by vector single instruction multiple data (SIMD) operations. This vector destination register load can be repeated if the tables store more used data. New data can be loaded into the original tables if appropriate. A level one memory is preferably partitioned as part data cache and part directly addressable memory. The look up table memory is stored in the directly addressable memory.

公开(公告)号：US20160125263A1

公开(公告)日：2016-05-05

申请号：US14931322

申请日：2015-11-03

Applicant: Texas Instruments Incorporated

Inventor： Jayasree Sankaranarayanan ,  Dipan Kumar Mandal

IPC: G06K9/52 ,  G06T7/60

CPC classification number: G06T7/60 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3887 ,  G06F9/3891 ,  G06F17/16 ,  G06T1/20 ,  G06T2200/28

Abstract: This invention forms a block sum of picture elements employing a vector dot product instruction to sum packed picture elements and the mask producing a vector of masked horizontal picture element. The block sum is formed from plural horizontal sums via vector single instruction multiple data (SIMD) addition.

Abstract translation: 本发明通过采用向量积积指令求和打包的图像元素和产生掩蔽的水平图像元素的矢量的掩模来形成图形元素的块和。 块和通过向量单指令多数据（SIMD）加法由多个水平和形成。