公开(公告)号：US20160344404A1

公开(公告)日：2016-11-24

申请号：US15160116

申请日：2016-05-20

Applicant: Texas Instruments Incorporated

Inventor： Eeshan MIGLANI ,  Karthikeyan Gunasekaran

IPC: H03M3/00

CPC classification number: H03M3/464 ,  H03M1/0665 ,  H03M1/66 ,  H03M3/424

Abstract: The disclosure provides a delta sigma modulator. The delta sigma modulator includes a summer. The summer generates an error signal in response to an input signal and a feedback signal. A loop filter is coupled to the summer and generates a filtered signal in response to the error signal. A quantizer is coupled to the loop filter and generates a quantized output signal in response to the filtered signal. A digital to analog converter (DAC) is coupled to the summer, and generates the feedback signal in response to a plurality of selection signals. A modified data weighted averaging (DWA) block is coupled between the quantizer and the DAC. The modified DWA block receives a clock signal and generates the plurality of selection signals in response to the quantized output signal and a primary coefficient. The primary coefficient varies with the clock signal.

Abstract translation: 本公开提供了一种Δ-Σ调制器。 ΔΣ调制器包括一个夏天。 夏天响应于输入信号和反馈信号产生误差信号。 环路滤波器耦合到加法器，并响应于误差信号产生滤波信号。 量化器耦合到环路滤波器并且响应于滤波的信号而产生量化的输出信号。 数模转换器（DAC）耦合到加法器，并响应于多个选择信号产生反馈信号。 在量化器和DAC之间耦合经修改的数据加权平均（DWA）块。 修改的DWA块接收时钟信号，并响应于量化的输出信号和一次系数而产生多个选择信号。 主要系数随时钟信号而变化。