公开(公告)号：US20230188138A1

公开(公告)日：2023-06-15

申请号：US17709734

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Lokesh Kumar Gupta ,  Upasana Bhattacharya

IPC: H03K19/0948 ,  H03K3/0233 ,  H04L12/40

CPC classification number: H03K19/0948 ,  H03K3/02337 ,  H04L12/4013 ,  H04L2012/40215

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed to buffer an input voltage. An example apparatus includes first inverter circuitry to invert the input voltage and produce a first inverted voltage; second inverter circuitry coupled to the first inverter circuitry, the second inverter circuitry to invert the first inverted voltage and produce a second inverted voltage at a rate based on a first current controlled transistor; third inverter circuitry coupled to the second inverter circuitry, the third inverter circuitry to invert the second inverted voltage and produce a third inverted voltage at a rate based on a second current controlled transistor; and fourth inverter circuitry coupled to the third inverter circuitry, the fourth inverter circuitry to invert the third inverted voltage and produce an output voltage, wherein the output voltage matches the input voltage.

公开(公告)号：US20200295755A1

公开(公告)日：2020-09-17

申请号：US16889939

申请日：2020-06-02

Applicant: Texas Instruments Incorporated

Inventor： Deep Banerjee ,  Lokesh Kumar Gupta ,  Somshubhra Paul

IPC: H03K17/687 ,  H04L12/40 ,  G05F3/26 ,  H03K17/16 ,  H03K17/30

Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.

公开(公告)号：US10707867B2

公开(公告)日：2020-07-07

申请号：US15834599

申请日：2017-12-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Deep Banerjee ,  Lokesh Kumar Gupta ,  Somshubhra Paul

IPC: H03K17/687 ,  G05F3/26 ,  H03K17/16 ,  H03K17/30 ,  H04L12/40

Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the gate voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the gate voltage at a second time rate that is smaller than the first time rate.

公开(公告)号：US10560282B2

公开(公告)日：2020-02-11

申请号：US15854583

申请日：2017-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeeth Aarey Premanath ,  Richard Edwin Hubbard ,  Maxwell Guy Robertson ,  Lokesh Kumar Gupta ,  Mark Edward Wentroble ,  Roland Sperlich ,  Dejan Radic

IPC: H04L12/40 ,  H04L12/12

Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.