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公开(公告)号：US11101794B2
公开(公告)日：2021-08-24
申请号：US16889939
申请日：2020-06-02
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Somshubhra Paul
IPC: H04L12/40 , G05F3/26 , H03K17/16 , H03K17/30 , H03K17/687
Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.
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公开(公告)号：US20230132605A1
公开(公告)日：2023-05-04
申请号：US17515804
申请日：2021-11-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jitender Kapil , Deep Banerjee
IPC: H03K19/017 , H03K19/17736 , H03K19/084 , H03K19/17784
Abstract: Structure and functionality reduce differential leakage current and compensate for differential capacitance discharge current from diode configurations to mitigate differential output polarity reversal that may occur in driver circuits. In an example driver circuit, one of two current sources coupled between a supply voltage and one output node is disabled during a driver disable time period (tpz) while the other continues to operate during a pre-charge monopulse time period (td) within tpz. A third current source on the other side of the driver circuit and coupled to ground is also disabled during tpz. During td, the following components are enabled: a charge current source coupled between the supply voltage and a second output node; a pair of current switches respectively coupled to the output nodes; and a pair of pull-down switches respectively coupled to control terminals of the current switches. After tpz, during a compensation time period (tcomp), the current sources enabled during to are disabled and a compensation current source is enabled. After tcomp, the compensation current source is disabled.
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公开(公告)号：US20200295755A1
公开(公告)日：2020-09-17
申请号：US16889939
申请日：2020-06-02
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Somshubhra Paul
IPC: H03K17/687 , H04L12/40 , G05F3/26 , H03K17/16 , H03K17/30
Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the control terminal voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the control terminal voltage at a second time rate that is smaller than the first time rate.
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公开(公告)号：US10707867B2
公开(公告)日：2020-07-07
申请号：US15834599
申请日：2017-12-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Somshubhra Paul
IPC: H03K17/687 , G05F3/26 , H03K17/16 , H03K17/30 , H04L12/40
Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the gate voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the gate voltage at a second time rate that is smaller than the first time rate.
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5.发明授权公开(公告)号：US12255680B2
公开(公告)日：2025-03-18
申请号：US17730451
申请日：2022-04-27
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Madhulatha Bonu , Vikas Thawani
Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.
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Patent Agency Ranking
公开(公告)号：US11967816B2
公开(公告)日：2024-04-23
申请号：US17244692
申请日：2021-04-29
Applicant: Texas Instruments Incorporated
Inventor： Ishaan Kubba , Sreeram Nasum Subramanyam , Shishir Goyal , Deep Banerjee
Abstract: An input/output (I/O) interface includes a resistance-to-current (R/I) converter; an internal resistor; first, second, and third current sources; first and second diodes; and a comparator. The R/I converter is coupled to an I/O pin and generates an output current based on an external resistance at the I/O pin during an analog operating mode. The internal resistor is coupled to the I/O pin and to ground. The first current source is coupled to the R/I converter circuit. The first diode is coupled to the R/I converter and to the I/O pin. The second current source is coupled to the R/I converter and the first diode and to ground. The second diode is coupled to the I/O pin and to the third current source. The comparator has inputs coupled to the I/O pin and to a reference voltage, and outputs a control signal indicative of a digital operating mode.
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公开(公告)号：US11863177B2
公开(公告)日：2024-01-02
申请号：US17515804
申请日：2021-11-01
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jitender Kapil , Deep Banerjee
IPC: H03K19/017 , H03K19/17784 , H03K19/084 , H03K19/17736
CPC classification number: H03K19/01742 , H03K19/084 , H03K19/1774 , H03K19/17784
Abstract: In an example driver circuit, one of two current sources coupled between a supply voltage and one output node is disabled during a driver disable time period (tpz) while the other continues to operate during a pre-charge monopulse time period (td) within tpz. A third current source on the other side of the driver circuit and coupled to ground is also disabled during tpz. During td, the following components are enabled: a charge current source coupled between the supply voltage and a second output node; a pair of current switches respectively coupled to the output nodes; and a pair of pull-down switches respectively coupled to control terminals of the current switches. After tpz, during a compensation time period (tcomp), the current sources enabled during td are disabled and a compensation current source is enabled. After tcomp, the compensation current source is disabled.
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8.发明公开公开(公告)号：US20230353185A1
公开(公告)日：2023-11-02
申请号：US17730451
申请日：2022-04-27
Applicant: Texas Instruments Incorporated
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Madhulatha Bonu , Vikas Thawani
CPC classification number: H04B1/405 , H04B1/44 , H04B1/0458 , H04B2001/0408
Abstract: A controller area network including one or more first network nodes biased from a first power supply voltage, and a second network node biased from a second, lower, power supply voltage. The second network node includes a transmitter driving a differential voltage onto bus lines to communicate a dominant bus state at a second dominant state common mode voltage, a receiver coupled to the bus lines, sense circuitry to sense a common mode voltage at the bus lines, and control circuitry to control a recessive state common mode voltage in response to the sensed dominant state common mode voltage.
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公开(公告)号：US11502716B2
公开(公告)日：2022-11-15
申请号：US17123915
申请日：2020-12-16
Applicant: TEXAS INSTRUMENTS INCORPORATED
Abstract: An on-off keying (OOK) receiver circuit includes a band-pass filter and an envelope detector. The band-pass filter includes a high-pass filter, a low-pass filter, and a switch. The high-pass filter is configured to filter an OOK input signal. The low-pass filter is configured to filter an output signal of the high-pass filter. The switch is coupled to an output of the high-pass filter, and is configured to, with each cycle of the OOK input signal, dissipate energy stored in the band-pass filter. The envelope detector is configured to receive a filtered OOK input signal from the band-pass filter, and to generate an OOK output signal based on the filtered OOK input signal.
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公开(公告)号：US20190131967A1
公开(公告)日：2019-05-02
申请号：US15834599
申请日：2017-12-07
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Deep Banerjee , Lokesh Kumar Gupta , Somshubhra Paul
IPC: H03K17/687 , G05F3/26
CPC classification number: H03K17/6871 , G05F3/262 , H03K17/163 , H03K17/302 , H04L12/4013 , H04L2012/40234
Abstract: A driver includes an open drain output transistor, a capacitor, a first current source, and first and second transistors. Upon assertion of a transmit signal to turn on the first transistor, a controller asserts a second control signal to turn on the second transistor responsive to a voltage of the capacitor being less than a threshold voltage of the open drain output transistor to thereby increase the gate voltage for the open drain output transistor at a first time rate. The controller deasserts the second control signal to turn off the second transistor responsive to the capacitor voltage exceeding the threshold voltage. Responsive to the capacitor's voltage exceeding the threshold, the first current source charges the capacitor to further increase the gate voltage at a second time rate that is smaller than the first time rate.
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