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公开(公告)号：US10560282B2
公开(公告)日：2020-02-11
申请号：US15854583
申请日：2017-12-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijeeth Aarey Premanath , Richard Edwin Hubbard , Maxwell Guy Robertson , Lokesh Kumar Gupta , Mark Edward Wentroble , Roland Sperlich , Dejan Radic
Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.
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公开(公告)号：US09602318B2
公开(公告)日：2017-03-21
申请号：US14819239
申请日：2015-08-05
Applicant: Texas Instruments Incorporated
Inventor： Roland Sperlich , Huanzhang Huang , Charles M. Branch
CPC classification number: H04L27/01 , H04B3/144 , H04L25/026 , H04L25/03019 , H04L25/03885
Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
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公开(公告)号：US20210159192A1
公开(公告)日：2021-05-27
申请号：US16697617
申请日：2019-11-27
Applicant: Texas Instruments Incorporated
IPC: H01L23/62 , H01L23/31 , H01L23/495
Abstract: A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.
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公开(公告)号：US20170257098A1
公开(公告)日：2017-09-07
申请号：US15600378
申请日：2017-05-19
Applicant: Texas Instruments Incorporated
Inventor： Weicheng Zhang , Huanzhang Huang , Yanli Fan , Roland Sperlich
IPC: H03K19/0944
CPC classification number: H03K19/0944 , H03K19/018578
Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.
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公开(公告)号：US20180351765A1
公开(公告)日：2018-12-06
申请号：US15854583
申请日：2017-12-26
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Abhijeeth Aarey Premanath , Richard Edwin Hubbard , Maxwell Guy Robertson , Lokesh Kumar Gupta , Mark Edward Wentroble , Roland Sperlich , Dejan Radic
CPC classification number: H04L12/40032 , H04L12/12 , H04L12/40039 , H04L2012/40215 , H04L2012/40273
Abstract: Two CAN bus transceivers utilized in a single integrated circuit package with the CAN bus connections between the two transceivers being inverted. Thus, one transceiver is connected to the CAN bus high and low lines while the other transceiver is connected to the CAN bus low and high lines. Both transceivers power up in a standby condition and each transceiver is monitoring for wake up signals on the CAN bus. The transceiver that is correctly connected to the CAN bus detects wake up signals. When the wake up signals are detected at that transceiver, that transceiver is brought to full operating state and the other transceiver is placed in a full standby condition. Additional input resistance is provided with each transceiver to maintain the proper input resistance for the integrated circuit.
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Patent Agency Ranking
公开(公告)号：US09660652B2
公开(公告)日：2017-05-23
申请号：US14847264
申请日：2015-09-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Weicheng Zhang , Huanzhang Huang , Yanli Fan , Roland Sperlich
IPC: H03K17/16 , H03K19/0944
CPC classification number: H03K19/0944 , H03K19/018578
Abstract: A driver includes first and second resistors coupled to a supply voltage and coupled to pairs of main transistors at positive and negative output nodes. The first and second pairs of main transistors provide emphasis and de-emphasis on the positive and negative output nodes. The driver also includes a delay inverter, a pull up booster and a pull down booster. The delay inverter delays and inverts each of a pair of differential input signals to provide delayed and inverted differential signals. The pull up booster provides a bypass current path that bypasses the first and second resistors but includes at least some of the first and second pairs of main transistors. The pull down booster provides an additional current path from the supply voltage through the first or second resistor to ground.
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公开(公告)号：US20140362900A1
公开(公告)日：2014-12-11
申请号：US14299187
申请日：2014-06-09
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Roland Sperlich , Huanzhang Huang , Charles M. Branch
IPC: H04L27/01
CPC classification number: H04L27/01 , H04B3/144 , H04L25/026 , H04L25/03019 , H04L25/03885
Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。
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公开(公告)号：US12051978B2
公开(公告)日：2024-07-30
申请号：US17813366
申请日：2022-07-19
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Dushmantha Bandara Rajapaksha , Roland Sperlich , Anant Shankar Kamath , Vijayalakshmi Devarajan , Wesley Ray
CPC classification number: H02M3/33523 , H01F27/288 , H02M1/4258 , H02M3/155 , H02M3/33569 , H02M3/33573 , H04L13/02 , H02M3/01
Abstract: A semiconductor package includes a transformer having a primary winding and a secondary winding. The primary winding has first and second terminals and a pair of taps. The secondary winding has first and second terminals and a pair of taps. The semiconductor package includes first and second data transfer circuits, a bridge, and a rectifier. The first data transfer circuit is coupled to the pair of taps of the primary winding. The second data transfer circuit is coupled to the pair of taps of the secondary winding. The bridge is coupled to the first and second terminals of the primary winding. The rectifier is coupled to the first and second terminals of the secondary winding.
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公开(公告)号：US11380631B2
公开(公告)日：2022-07-05
申请号：US16697617
申请日：2019-11-27
Applicant: Texas Instruments Incorporated
IPC: H01L23/62 , H01L23/31 , H01L23/495
Abstract: A lead frame for a multi-chip module includes a first conductor structure disposed on a substrate and having first and second arms linked at an angle. The first conductor structure is connected to ground. The lead frame also includes a second conductor structure disposed on the substrate and connected to a voltage supply. The second conductor structure is spaced apart and electrically isolated from the first conductor structure. The first and the second conductor structures are arranged to flank a plurality of integrated circuits (ICs) including one or more surge protection ICs disposed on the substrate. The first conductor structure is electrically connected to the plurality of ICs to provide electrical connections to ground, and the second conductor structure is electrically connected to the plurality of ICs to provide electrical connections to the voltage supply.
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公开(公告)号：US20150341194A1
公开(公告)日：2015-11-26
申请号：US14819239
申请日：2015-08-05
Applicant: Texas Instruments Incorporated
Inventor： Roland Sperlich , Huanzhang Huang , Charles M. Branch
CPC classification number: H04L27/01 , H04B3/144 , H04L25/026 , H04L25/03019 , H04L25/03885
Abstract: A serial communication circuit (FIG. 3) is disclosed. The circuit includes an equalizer circuit (306) arranged to receive a data signal (CH 1) and produce an equalized data signal. A log detector circuit (300) receives the data signal and produces a power signal indicating a power level of the data signal. A decision circuit (332) receives the power signal and produces a select signal. A first selection circuit (336) receives a plurality of first correction signals and applies one of the first correction signals to the equalizer circuit in response to the select signal.
Abstract translation: 公开了串行通信电路（图3）。 电路包括均衡器电路（306），其布置成接收数据信号（CH 1）并产生均衡的数据信号。 对数检测器电路（300）接收数据信号并产生指示数据信号的功率电平的功率信号。 判定电路（332）接收电力信号并产生选择信号。 第一选择电路（336）接收多个第一校正信号，并且响应于选择信号将第一校正信号中的一个施加到均衡器电路。
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