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    SEMICONDUCTOR DEVICE AND PROCESS WITH CRACK REDUCTION
    15.
    发明申请
    SEMICONDUCTOR DEVICE AND PROCESS WITH CRACK REDUCTION 有权

    公开(公告)号：US20250046733A1

    公开(公告)日：2025-02-06

    申请号：US18362894

    申请日：2023-07-31

    Applicant: Texas Instruments Incorporated

    Inventor： Jaimal Mallory Willamson ,  Michael Todd Wyant ,  Yutaka Suzuki

    IPC: H01L23/00 ,  H01L21/78 ,  H01L23/31

    Abstract: An example device includes: a semiconductor die formed on a semiconductor substrate and having a device side surface, a backside surface opposite the device side surface, and having sides between the device side surface and the backside surface at edges of the semiconductor die; the semiconductor die having a device area comprising electrical devices formed on the semiconductor die, and having a scribe spacing area between the device area and the edges of the semiconductor die; the semiconductor die having polymeric anchors in the scribe spacing area, the polymeric anchors being recesses that extend through a protective overcoat dielectric layer that is over the device side surface of the semiconductor die, and extending into the semiconductor substrate of the semiconductor die; and polymeric material covering at least a portion of the semiconductor die, the polymeric material filling the recesses of the polymeric anchors.

    Integrated circuit with metal stop ring outside the scribe seal
    16.
    发明授权
    Integrated circuit with metal stop ring outside the scribe seal 有权

    公开(公告)号：US12009319B2

    公开(公告)日：2024-06-11

    申请号：US16737237

    申请日：2020-01-08

    Applicant: Texas Instruments Incorporated

    Inventor： Christopher Daniel Manack ,  Qiao Chen ,  Michael Todd Wyant ,  Matthew John Sherbin ,  Patrick Francis Thompson

    IPC: H01L23/58 ,  H01L23/528 ,  H01L23/532

    CPC classification number: H01L23/585 ,  H01L23/528 ,  H01L23/53209

    Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

    METHODS OF SEPARATING SEMICONDUCTOR DIES
    17.
    发明公开
    METHODS OF SEPARATING SEMICONDUCTOR DIES 审中-公开

    公开(公告)号：US20240071828A1

    公开(公告)日：2024-02-29

    申请号：US17823797

    申请日：2022-08-31

    Applicant: Texas Instruments Incorporated

    Inventor： Michael Todd Wyant

    IPC: H01L21/784 ,  H01L21/02 ,  H01L21/3065 ,  H01L23/50

    CPC classification number: H01L21/784 ,  H01L21/0206 ,  H01L21/02096 ,  H01L21/3065 ,  H01L23/50

    Abstract: Methods of separating semiconductor dies are described. The method can separate individual semiconductor dies from a semiconductor wafer without using a blade. The methods include a plasma etch process utilizing metal structures formed on a back side of the wafer as masks to remove a portion of the semiconductor wafer from the back side. The portion removed by the plasma etch process corresponds to the scribe lines between the semiconductor dies. The plasma etch process terminates at a dielectric layer formed on a front side of the wafer. The dielectric layer may be severed to complete the separation process. Moreover, an ultrasonic water jet process may be utilized to remove burrs of the dielectric layer that has been severed.

    Laser dicing for singulation
    18.
    发明授权
    Laser dicing for singulation 有权

    公开(公告)号：US11469141B2

    公开(公告)日：2022-10-11

    申请号：US16057126

    申请日：2018-08-07

    Applicant: Texas Instruments Incorporated

    Inventor： Michael Todd Wyant ,  Dave Charles Stepniak ,  Matthew John Sherbin ,  Sada Hiroyuki ,  Shoichi Iriguchi ,  Genki Yano

    IPC: H01L21/78 ,  H01L23/58 ,  H01L21/683 ,  H01L21/67 ,  H01L21/268

    Abstract: In a described example, a method includes: applying a dicing tape over a metal layer covering a portion of a surface of scribe streets on a device side of a semiconductor wafer that includes semiconductor device dies formed thereon separated from one another by the scribe streets; and placing the semiconductor wafer with the device side facing away from a laser in a stealth dicing machine. A power of a laser beam is adjusted to a first power level. The laser beam is focused through the non-device side of the semiconductor wafer to a first focal depth in the metal layer. The laser beam scans across the scribe streets and ablates the metal layer in the scribe streets. The method continues by singulating the semiconductor device dies using stealth dicing along the scribe streets in the stealth dicing machine.

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