公开(公告)号：US12002846B2

公开(公告)日：2024-06-04

申请号：US17500096

申请日：2021-10-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  David Matthew Curran ,  Stephen Arlon Meisner ,  Bhaskar Srinivasan ,  Guruvayurappan S. Mathur ,  Scott William Jessen ,  Shih Chang Chang ,  Russell Duane Fields ,  Thomas Terrance Lynch

IPC: H01L21/02 ,  H01L49/02

CPC classification number: H01L28/60 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02274

Abstract: In some examples, an integrated circuit comprises a substrate; a first metal layer and a second metal layer positioned above the substrate; a first composite dielectric layer located on the first metal layer, wherein the first composite dielectric layer comprises a first anti-reflective coating; a second composite dielectric layer positioned on the second metal layer, wherein the second composite dielectric layer comprises a second anti-reflective coating; and a capacitor metal layer disposed over the first composite dielectric layer.

公开(公告)号：US20190157379A1

公开(公告)日：2019-05-23

申请号：US16240194

申请日：2019-01-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

IPC: H01L49/02 ,  H01L21/768 ,  H01L21/02 ,  H01L27/108 ,  H01L29/16 ,  H01L27/06 ,  H01L29/66

Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

公开(公告)号：US11094644B2

公开(公告)日：2021-08-17

申请号：US16679997

申请日：2019-11-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Adrian Salinas ,  William Keith McDonald ,  Scott Alexander Johannesmeyer ,  Robert Paul Luckin ,  Stephen Arlon Meisner

IPC: G03F7/20 ,  H01L21/027 ,  H01L23/544

Abstract: In examples, a method of manufacturing an integrated circuit comprises locating a photomask between a light source and a semiconductor wafer having a photoresist layer in a wafer scribe lane of the wafer, wherein the photomask comprises: a first mask scribe lane pattern; a second mask scribe lane pattern matching the first mask scribe lane pattern; and at least one circuit pattern of the integrated circuit located between the first and second mask scribe lane patterns. The method further includes illuminating the photomask to produce in the photoresist layer of the wafer scribe lane a first exposed portion corresponding to the second mask scribe lane pattern; locating the first mask scribe lane pattern between the light source and the first exposed portion; and illuminating the photomask, wherein the first mask scribe lane pattern substantially shields non-exposed portions of the photoresist layer of the wafer scribe lane from light exposure.

公开(公告)号：US20230134102A1

公开(公告)日：2023-05-04

申请号：US17514313

申请日：2021-10-29

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Stephen Arlon Meisner ,  James Thomas Hallowell ,  Michael Todd Wyant

IPC: H01L23/544

Abstract: A photo alignment structure is provided that includes a wafer having scribe lines defined therein in a top planar surface of the wafer. An alignment structure is disposed on a top planar surface of the wafer longitudinally aligned with a portion of selected scribe lines, where the alignment structure is comprised of metal layers. A slot is defined along a longitudinal axis of the alignment structure in at least one of the metal layers.

公开(公告)号：US10608075B2

公开(公告)日：2020-03-31

申请号：US16240194

申请日：2019-01-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/66 ,  H01L27/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/768 ,  H01L21/027 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522 ,  H01L29/94

Abstract: An integrated circuit includes a capacitor located over a semiconductor substrate. The capacitor includes a first conductive layer having a first lateral perimeter, and a second conductive layer having a second smaller lateral perimeter. A first dielectric layer is located between the second conductive layer and the first conductive layer. The first dielectric layer has a thinner portion having the first lateral perimeter and a thicker portion having the second lateral perimeter. An interconnect line is located over the substrate, and includes a third conductive layer that is about coplanar with and has about a same thickness as the first conductive layer. A second dielectric layer is located over the third conductive layer. The second dielectric layer is about coplanar with and has about a same thickness as the thinner portion of the first dielectric layer.

公开(公告)号：US10177215B1

公开(公告)日：2019-01-08

申请号：US15793690

申请日：2017-10-25

Applicant: Texas Instruments Incorporated

Inventor： Bhaskar Srinivasan ,  Guru Mathur ,  Stephen Arlon Meisner ,  Shih Chang Chang ,  Corinne Ann Gagnet

IPC: H01L49/02 ,  H01L27/108 ,  H01L29/66 ,  H01L27/06 ,  H01L29/16 ,  H01L21/02 ,  H01L21/768 ,  H01L29/94

Abstract: A microelectronic device includes a capacitor having a lower plate of interconnect metal, a capacitor dielectric layer with a lower silicon dioxide layer, a silicon oxy-nitride layer, and an upper silicon dioxide layer, and an upper plate over the capacitor dielectric layer. The silicon oxy-nitride layer has an average index of refraction of 1.85 to 1.95 at a wavelength of 248 nanometers. To form the microelectronic device, the lower silicon dioxide layer, the silicon oxy-nitride layer, and the upper silicon dioxide layer are formed in sequence over an interconnect metal layer. The upper plate is formed, leaving the lower silicon dioxide layer, the silicon oxy-nitride layer, and at least a portion of the upper silicon dioxide layer over the interconnect metal layer. An interconnect mask is formed of photoresist over the upper plate and the silicon oxy-nitride layer, using the silicon oxy-nitride layer as an anti-reflection layer.