公开(公告)号：US20190259717A1

公开(公告)日：2019-08-22

申请号：US15901631

申请日：2018-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L21/78

Abstract: A packaged semiconductor die includes a semiconductor die coupled to a die pad. The semiconductor die has a front side containing copper leads, a copper seed layer coupled to the copper leads, and a nickel alloy coating coupled to the copper seed layer. The nickel alloy includes tungsten and cerium (NiWCe). The packaged semiconductor die may also include wire bonds coupled between leads of a lead frame and the copper leads of the semiconductor die. In addition, the packaged semiconductor die may be encapsulated in molding compound. A method for fabricating a packaged semiconductor die. The method includes forming a copper seed layer over the copper leads of the semiconductor die. In addition, the method includes coating the copper seed layer with a nickel alloy. The method also includes singulating the semiconductor wafer to create individual semiconductor die and placing the semiconductor die onto a die pad of a lead frame. In addition the method includes wire bonding the leads of a lead frame to the copper leads of the semiconductor die and then encapsulating the die in molding compound.

公开(公告)号：US20190109074A1

公开(公告)日：2019-04-11

申请号：US15984343

申请日：2018-05-19

Applicant: Texas Instruments Incorporated

Inventor： Christopher Daniel Manack ,  Nazila Dadvand ,  Salvatore Frank Pavone

IPC: H01L23/495 ,  H01L23/532 ,  H01L23/49 ,  H01L23/492 ,  H01L23/00

Abstract: A microelectronic device is formed by thinning a substrate of the microelectronic device from a die attach surface of the substrate, and forming a copper-containing layer on the die attach surface of the substrate. A protective metal layer is formed on the copper-containing layer. Subsequently, the copper-containing layer is attached to a package member having a package die mount area. The protective metal layer may optionally be removed prior to attaching the copper-containing layer to the package member. Alternatively, the protective metal layer may be left on the copper-containing layer when the copper-containing layer is attached to the package member. A structure formed by the method is also disclosed.

公开(公告)号：US12237219B2

公开(公告)日：2025-02-25

申请号：US17038947

申请日：2020-09-30

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532

Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

公开(公告)号：US11935821B2

公开(公告)日：2024-03-19

申请号：US17210392

申请日：2021-03-23

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/28 ,  H01L23/532 ,  H05K3/34

CPC classification number: H01L23/49582 ,  H01L23/28 ,  H01L23/4951 ,  H01L23/49541 ,  H01L23/49575 ,  H01L23/53233 ,  H01L24/97 ,  H05K3/3442

Abstract: A device and method for fabrication thereof is provided which results in corrosion resistance of metal flanges (802) of a semiconductor package, such as a quad flat no-lead package (QFN). Using metal electroplating (such as electroplating of nickel (Ni) or nickel alloys on copper flanges of the QFN package), corrosion resistance for the flanges is provided using a process that allows an electric current to reach the entire backside of a substrate (102) to permit electroplating. In addition, the method may be used to directly connect a semiconductor die (202) to the metal substrate (102) of the package.

公开(公告)号：US20230123307A1

公开(公告)日：2023-04-20

申请号：US17504182

申请日：2021-10-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand

IPC: H01L23/00

Abstract: A system and method for etching a die in a tin (Sn) electrolyte. The die includes a silicon wafer and a diffusion barrier disposed on the silicon wafer. A copper seed layer disposed on the diffusion barrier and at least one copper bump bond is disposed on a portion of the copper seed layer. A tin layer is disposed on side walls of the at least one copper bump bond. The tin layer inhibits etching of the side walls of the at least one copper bump bond during an etching process to the copper seed layer to remove exposed portions of the copper seed layer.

公开(公告)号：US20230114872A1

公开(公告)日：2023-04-13

申请号：US17710920

申请日：2022-03-31

Applicant: Texas Instruments Incorporated

Inventor： Nazila Dadvand

IPC: H01L23/495 ,  H01L21/48

Abstract: An electronic device includes a package structure and a conductive lead with a first surface and a second surface. The first surface has a first plated layer exposed outside the package structure along a first side of the package structure, and the second surface has a second plated layer exposed along the bottom side of the package structure. A method includes forming a first plated layer on a first surface of a conductive lead exposed along a bottom side of a molded structure in a panel array, performing a package separation process that separates an electronic device from the panel array, placing the bottom side of the package structure and the first plated layer on a tape layer above a conductive plate, and forming a second plated layer on the exposed second surface of the conductive lead.

公开(公告)号：US11443996B2

公开(公告)日：2022-09-13

申请号：US15909679

申请日：2018-03-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Keith Edward Johnson ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.

公开(公告)号：US20220208665A1

公开(公告)日：2022-06-30

申请号：US17139985

申请日：2020-12-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Nazila Dadvand ,  Bernardo Gallegos

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.

公开(公告)号：US11355414B2

公开(公告)日：2022-06-07

申请号：US16586720

申请日：2019-09-27

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nazila Dadvand ,  Daniel Lee Revier ,  Archana Venugopal

IPC: H01L23/373 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L21/285

Abstract: In described examples, a circuit (e.g., an integrated circuit) includes a semiconductor substrate that includes a frontside surface and a backside surface. A circuit element is included at the frontside surface. An optional electrical insulator layer can be included adjacent to the backside surface. A distributor layer is included adjacent to the backside surface. In some examples, the distributor layer includes a distributor material that includes a matrix of cohered nanoparticles and metallic particles embedded by the cohered nanoparticles.

公开(公告)号：US11309388B2

公开(公告)日：2022-04-19

申请号：US16995563

申请日：2020-08-17

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Luigi Colombo ,  Nazila Dadvand ,  Archana Venugopal

IPC: H01L29/15 ,  H01L29/16 ,  H01L29/423 ,  H01L29/808 ,  H01L29/66

Abstract: A switchable array includes: a microstructure of interconnected units formed of graphene tubes with open spaces in the microstructure bounded by the graphene tubes; at least one JFET gate in at least one of the graphene tubes; and a control line having an end connected to the at least one JFET gate. The control line extends to a periphery of the microstructure.