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    Contact with bronze material to mitigate undercut
    1.
    发明授权
    Contact with bronze material to mitigate undercut 有权

    公开(公告)号：US12237219B2

    公开(公告)日：2025-02-25

    申请号：US17038947

    申请日：2020-09-30

    Applicant: Texas Instruments Incorporated

    Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

    IPC: H01L23/00 ,  H01L21/768 ,  H01L23/532

    Abstract: Described examples provide microelectronic devices and fabrication methods, including fabricating a contact structure by forming a titanium or titanium tungsten barrier layer on a conductive feature, forming a tin seed layer on the barrier layer, forming a copper structure on the seed layer above the conductive feature of the wafer or die, heating the seed layer and the copper structure to form a bronze material between the barrier layer and the copper structure, removing the seed layer using an etching process that selectively removes an exposed portion of the seed layer, and removing an exposed portion of the barrier layer.

    Three dimensional package for semiconductor devices and external components
    4.
    发明授权
    Three dimensional package for semiconductor devices and external components 有权

    公开(公告)号：US11631632B2

    公开(公告)日：2023-04-18

    申请号：US17135700

    申请日：2020-12-28

    Applicant: Texas Instruments Incorporated

    Inventor： Christopher Daniel Manack ,  Sreenivasan Kalyani Koduri

    IPC: H01L23/495 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48

    Abstract: In a described example, an apparatus includes: a package substrate having a die mount portion and lead portions; at least one semiconductor device die over the die mount portion of the package substrate, the semiconductor device die having bond pads on an active surface facing away from the package substrate; electrical connections between at least one of the bond pads and one of the lead portions; a post interconnect over at least one of the bond pads, the post interconnect extending away from the active surface of the semiconductor device die; and a dielectric material covering a portion of the package substrate, the semiconductor device die, a portion of the post interconnect, and the electrical connections, forming a packaged semiconductor device, wherein the post interconnect extends through the dielectric material and had an end facing away from the semiconductor device die that is exposed from the dielectric material.

    Zinc layer for a semiconductor die pillar
    5.
    发明授权
    Zinc layer for a semiconductor die pillar 有权

    公开(公告)号：US11443996B2

    公开(公告)日：2022-09-13

    申请号：US15909679

    申请日：2018-03-01

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Nazila Dadvand ,  Keith Edward Johnson ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

    IPC: H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

    Abstract: A method for fabricating a copper pillar. The method includes forming a layer of titanium tungsten (TiW) over a semiconductor wafer, forming a layer of zinc (Zn) over the layer of TiW, and forming a copper pillar over the via. In addition, the method includes performing an anneal to diffuse the layer of Zn into the copper pillar. A semiconductor device that includes a layer of TiW coupled to a via of a semiconductor wafer and a copper pillar coupled to the layer of TiW. The copper pillar has interdiffused Zn within its bottom portion. Another method for fabricating a copper pillar includes forming a layer of TiW over a semiconductor wafer, forming a first patterned photoresist, forming a layer of Zn, and then removing the first patterned photoresist. The method further includes forming a second patterned photoresist and forming a copper pillar.

    Efficient redistribution layer topology
    6.
    发明授权
    Efficient redistribution layer topology 有权

    公开(公告)号：US11380637B2

    公开(公告)日：2022-07-05

    申请号：US16950708

    申请日：2020-11-17

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Vivek Swaminathan Sridharan ,  Christopher Daniel Manack ,  Joseph Liu

    IPC: H01L23/00

    Abstract: In some examples, a chip scale package (CSP) comprises a semiconductor die; a passivation layer abutting the semiconductor die; a via extending through the passivation layer; and a first metal layer abutting the via. The CSP also includes an insulation layer abutting the first metal layer, with the insulation layer having an orifice with a maximal horizontal area of less than 32400 microns2. The CSP further includes a second metal layer abutting the insulation layer and adapted to couple to a solder ball. The second metal layer abuts the first metal layer at a point of contact defined by the orifice in the insulation layer.

    Nanostructure barrier for copper wire bonding
    8.
    发明授权
    Nanostructure barrier for copper wire bonding 有权

    公开(公告)号：US11127515B2

    公开(公告)日：2021-09-21

    申请号：US16854839

    申请日：2020-04-21

    Applicant: Texas Instruments Incorporated

    Inventor： Nazila Dadvand ,  Christopher Daniel Manack ,  Salvatore Frank Pavone

    IPC: H01L23/00 ,  H01B13/00 ,  H01B1/02

    Abstract: A nanostructure barrier for copper wire bonding includes metal grains and inter-grain metal between the metal grains. The nanostructure barrier includes a first metal selected from nickel or cobalt, and a second metal selected from tungsten or molybdenum. A concentration of the second metal is higher in the inter-grain metal than in the metal grains. The nanostructure barrier may be on a copper core wire to provide a coated bond wire. The nanostructure barrier may be on a bond pad to form a coated bond pad. A method of plating the nanostructure barrier using reverse pulse plating is disclosed. A wire bonding method using the coated bond wire is disclosed.

    INTEGRATED CIRCUIT WITH METAL STOP RING OUTSIDE THE SCRIBE SEAL
    9.
    发明申请
    INTEGRATED CIRCUIT WITH METAL STOP RING OUTSIDE THE SCRIBE SEAL 有权

    公开(公告)号：US20210210440A1

    公开(公告)日：2021-07-08

    申请号：US16737237

    申请日：2020-01-08

    Applicant: Texas Instruments Incorporated

    Inventor： Christopher Daniel Manack ,  Qiao Chen ,  Michael Todd Wyant ,  Matthew John Sherbin ,  Patrick Francis Thompson

    IPC: H01L23/58 ,  H01L23/532 ,  H01L23/528

    Abstract: An integrated circuit (IC) die includes a substrate with circuitry configured for at least one function including metal interconnect levels thereon including a top metal interconnect level and a bottom metal interconnect level, with a passivation layer on the top metal interconnect level. A scribe street is around a periphery of the IC die, the scribe street including a scribe seal utilizing at least two of the plurality of metal interconnect levels, an inner metal meander stop ring including at least the top metal interconnect level located outside the scribe seal, wherein the scribe seal and the inner metal meander stop ring are separated by a first separation gap. An outer metal meander stop ring including at least the top metal interconnect level is located outside the inner metal stop ring, wherein the outer stop ring and the inner stop ring are separated by a second separation gap.

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