公开(公告)号：US20160191383A1

公开(公告)日：2016-06-30

申请号：US15059340

申请日：2016-03-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart

IPC: A61B19/00 ,  H04L29/12 ,  H04N19/10

CPC classification number: H04L45/741 ,  H04L61/251 ,  H04L61/6004 ,  H04L61/6095

Abstract: In an embodiment of the invention, a method of performing a byte-rotate-merge on computer hardware is discussed. Byte-rotating is performed on first and second source operands and are byte-rotated by first and second rotation constants respectively. The first byte-rotate output and the second byte-rotate output are merged. Bytes from the first byte-rotate output are output to a byte-rotate-merge output when control bits from a byte-mask are logical ones. Bytes from the second byte-rotate output are output to a byte-rotate-merge output when control bits from the byte-mask are logical zeros.

Abstract translation: 在本发明的实施例中，讨论了在计算机硬件上执行字节旋转合并的方法。 在第一和第二源操作数上执行字节旋转，并分别由第一和第二旋转常数进行字节旋转。 第一个字节旋转输出和第二个字节旋转输出合并。 来自字节掩码的控制位是逻辑1时，来自第一个字节旋转输出的字节被输出到一个字节旋转合并输出。 来自字节掩码的控制位为逻辑0时，来自第二字节旋转输出的字节被输出到字节旋转合并输出。

公开(公告)号：US20140334489A1

公开(公告)日：2014-11-13

申请号：US14072989

申请日：2013-11-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/875 ,  H04L12/741

CPC classification number: H04L47/56 ,  H04L45/24 ,  H04L45/745 ,  H04L69/22

Abstract: An embodiment of the invention includes a packet processing pipeline. The packet processing pipeline includes match and action stages. Each match and action stage in incurs a match delay when match processing occurs and each match and action stage incurs an action delay when action processing occurs. A transport delay occurs between successive match and action stages when data is transferred from a first match and action stage to a second match and action stage.

Abstract translation: 本发明的实施例包括分组处理流水线。 分组处理流水线包括匹配和动作阶段。 当匹配处理发生时，每个匹配和动作阶段引起匹配延迟，并且当发生动作处理时，每个匹配和动作阶段引起动作延迟。 当数据从第一个匹配和动作阶段转移到第二个匹配和动作阶段时，在连续匹配和动作阶段之间发生传输延迟。

公开(公告)号：US20140241358A1

公开(公告)日：2014-08-28

申请号：US14190734

申请日：2014-02-26

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/743

CPC classification number: H04L45/7453 ,  G06F9/3853 ,  H04L45/7457

Abstract: An embodiment of the invention includes receiving packet header vectors where a header vector includes a number of packet header words. Match operations are performed on the packet header words. At least one packet header word is modified based on the match operations. At least one processor is used for each packet header word to perform the packet match operations and modify at least one packet header word. Instructions are received from an instruction word where a VLIW instruction word includes all of the instruction words. Each processor performs an operation in response to the instruction word.

Abstract translation: 本发明的实施例包括接收分组报头向量，其中报头向量包括多个分组报头字。 对分组头文字执行匹配操作。 基于匹配操作来修改至少一个分组报头字。 对于每个分组报头字使用至少一个处理器来执行分组匹配操作并修改至少一个分组报头字。 从VLIW指令字包括所有指令字的指令字接收指令。 每个处理器响应于指令字执行操作。

公开(公告)号：US10785151B2

公开(公告)日：2020-09-22

申请号：US15906944

申请日：2018-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart

IPC: H04L12/741 ,  H04L12/707 ,  H04L12/771

Abstract: An embodiment includes a plurality of tables in a hardware network for performing packet processing. Each table in the plurality of tables includes a table declaration. The table declaration includes a first set of fields used for input matching and a second set of fields used as inputs for action processing. A first table is selected from the plurality of tables. Successor tables to the first table are selected from the plurality of tables. There is a third set of fields for each successor table of the successor tables. The contents of the third set of fields are output fields where the output fields are modified by the first table when a next table of the first table is the successor table of the first table.

公开(公告)号：US10033626B2

公开(公告)日：2018-07-24

申请号：US15062245

申请日：2016-03-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart

IPC: H04L12/28 ,  H04L12/733 ,  H04L12/741 ,  H04L12/723

Abstract: A network switch includes a plurality of ports, a parser coupled to the plurality of ports, and a processor coupled to the ports and configured to process a received packet via one of the ports. The received packet includes a first header field, a second header field, and a destination header field, each of the first, second, and destination header fields including a TTL field. The parser is configured to decide a valid bit for each of the first header field, the second header field and the destination header field, based on an availability for each of the first header field, the second header field and the destination header field. The processor is configured to execute an instruction to cause content of a select one of the first or second header field's TTL field to be copied to the destination header field.

公开(公告)号：US20180191613A1

公开(公告)日：2018-07-05

申请号：US15906944

申请日：2018-02-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart

IPC: H04L12/741 ,  H04L12/707 ,  H04L12/771

Abstract: An embodiment includes a plurality of tables in a hardware network for performing packet processing. Each table in the plurality of tables includes a table declaration. The table declaration includes a first set of fields used for input matching and a second set of fields used as inputs for action processing. A first table is selected from the plurality of tables. Successor tables to the first table are selected from the plurality of tables. There is a third set of fields for each successor table of the successor tables. The contents of the third set of fields are output fields where the output fields are modified by the first table when a next table of the first table is the successor table of the first table.

公开(公告)号：US09998574B2

公开(公告)日：2018-06-12

申请号：US15788179

申请日：2017-10-19

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/701 ,  H04L29/06 ,  H04L12/741

CPC classification number: H04L69/22 ,  H04L45/00 ,  H04L45/74

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

公开(公告)号：US09826067B2

公开(公告)日：2017-11-21

申请号：US14193190

申请日：2014-02-28

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart ,  Hun-Seok Kim

IPC: H04L12/701 ,  H04L29/06 ,  H04L12/741

CPC classification number: H04L69/22 ,  H04L45/00 ,  H04L45/74

Abstract: A packet processing block. The block has an input for receiving data in a packet header vector, the vector comprising data representing information for a packet and a match unit for performing match operations between packet header vector data and at least one match table. Various embodiments provide advantages in connection with storing certain action or next table bits outside of the match table, or constants in the table, or by forming the match table from multiple unit match table memories.

公开(公告)号：US09087585B2

公开(公告)日：2015-07-21

申请号：US14205780

申请日：2014-03-12

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart

IPC: G11C15/00 ,  G11C15/04

CPC classification number: G11C15/04

Abstract: An embodiment of the invention includes a ternary content addressable memory (TCAM) that has input search data bits, TCAM words and range search input data bits. Each TCAM word is operable to store a match pattern and provide a match output. The match output indicates a match when the match pattern of the TCAM word matches the TCAM input search data bits. The range search input data bits are separated into groups. Each group has a bit width N where N is the number of range search input data bits. For the match pattern in each group, there is a Boolean function that uses the N range of search input data bits. (2N)/2 TCAM bits are provided for each TCAM word. 2N internal TCAM search lines are operable to search the (2N)/2 TCAM bits. Decoder logic is associated with each group that decodes the N range search input data bits.

Abstract translation: 本发明的实施例包括具有输入搜索数据位，TCAM字和范围搜索输入数据位的三元内容可寻址存储器（TCAM）。 每个TCAM字可操作地存储匹配模式并提供匹配输出。 匹配输出表示当TCAM字符的匹配模式与TCAM输入搜索数据位匹配时的匹配。 范围搜索输入数据位被分成组。 每组具有位宽N，其中N是范围搜索输入数据位的数量。 对于每个组中的匹配模式，有一个使用N个搜索输入数据位范围的布尔函数。 （2N）/ 2个TCAM位为每个TCAM字提供。 2N内部TCAM搜索行可以搜索（2N）/ 2个TCAM位。 解码器逻辑与解码N个范围搜索输入数据位的每个组相关联。

公开(公告)号：US20140268972A1

公开(公告)日：2014-09-18

申请号：US14205812

申请日：2014-03-12

Applicant: Texas Instruments Incorporated

Inventor： Patrick W. Bosshart

IPC: G11C15/04

CPC classification number: G11C15/04

Abstract: An embodiment of the invention includes first and second Ternary Content Addressable Memories (TCAMs), a first vector, and TCAM match-merge unit. Each of the TCAMs includes a plurality of words, stores TCAM match entries and outputs a TCAM match signal for each word in the plurality of words. The first vector includes first TCAM group enable register bits. An enabling value on the first TCAM register bit indicates that the first TCAM match signal and the neighboring first TCAM match are in the same TCAM group. The TCAM match-merge unit receives the first TCAM match signal from each of the words and the first vector and outputs a first TCAM group match signal for each of the words. The TCAM match-merge unit outputs a match indication when any of the TCAM match signals indicate a match and outputs a mismatch when none of the TCAM match signals match.

Abstract translation: 本发明的实施例包括第一和第二三进制内容可寻址存储器（TCAM），第一向量和TCAM匹配合并单元。 每个TCAM包括多个字，存储TCAM匹配项，并输出多个单词中的每个单词的TCAM匹配信号。 第一个向量包括第一个TCAM组使能寄存器位。 第一个TCAM寄存器位的使能值表示第一个TCAM匹配信号和相邻的第一个TCAM匹配位于相同的TCAM组中。 TCAM匹配合并单元从每个单词和第一矢量接收第一TCAM匹配信号，并输出每个单词的第一TCAM组匹配信号。 当任何TCAM匹配信号指示匹配时，TCAM匹配合并单元输出匹配指示，并且当没有TCAM匹配信号匹配时输出失配。