公开(公告)号：US11710764B2

公开(公告)日：2023-07-25

申请号：US16020131

申请日：2018-06-27

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Sagnik Dey ,  Luigi Colombo ,  Haowen Bu ,  Scott Robert Summerfelt ,  Mark Robert Visokay ,  John Paul Campbell

IPC: H01L21/285 ,  H01L49/02 ,  H01L21/3213 ,  H01L21/306

CPC classification number: H01L28/91 ,  H01L21/28518 ,  H01L21/306 ,  H01L21/32133

Abstract: An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

公开(公告)号：US11605587B2

公开(公告)日：2023-03-14

申请号：US16383176

申请日：2019-04-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Bhaskar Srinivasan ,  Scott William Jessen ,  Guruvayurappan S. Mathur

IPC: H01L23/522 ,  H01L49/02 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

Abstract: In some examples, a method comprises: obtaining a substrate having at a metal interconnect layer deposited over the substrate; forming a first dielectric layer on the metal interconnect layer; forming a second dielectric layer on the first dielectric layer; forming a capacitor metal layer on the second dielectric layer; patterning and etching the capacitor metal layer and the second dielectric layer to the first dielectric layer to leave a portion of the capacitor metal layer and the second dielectric layer on the first dielectric layer; forming an anti-reflective coating to cover the portion of the capacitor metal layer and the second dielectric layer, and to cover the metal interconnect layer; and patterning the metal interconnect layer to form a first metal layer and a second metal layer.

公开(公告)号：US11587864B2

公开(公告)日：2023-02-21

申请号：US17540447

申请日：2021-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Ye Shao ,  Guruvayurappan S. Mathur ,  John K. Arch ,  Paul Stulik

IPC: H01L21/00 ,  H01L23/522 ,  H01G15/00 ,  H01G4/06

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

公开(公告)号：US11222841B2

公开(公告)日：2022-01-11

申请号：US16561593

申请日：2019-09-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Poornika Fernandes ,  Ye Shao ,  Guruvayurappan S. Mathur ,  John K. Arch ,  Paul Stulik

IPC: H01L21/00 ,  H01L23/522 ,  H01G15/00 ,  H01G4/06

Abstract: An integrated circuit (IC) includes a substrate and a first capacitor on the substrate. The first capacitor has a first width. A first dielectric layer is provided on a side of the first capacitor opposite the substrate. Further, a second capacitor is present on a side of the first dielectric layer opposite the first capacitor. The second capacitor has a second width that is smaller than the first width. The IC also has a second dielectric layer and a first metal layer. The second dielectric layer is on a side of the second capacitor opposite the first dielectric layer. The first metal layer is on a side of the second dielectric layer opposite the second capacitor.

公开(公告)号：US20210202688A1

公开(公告)日：2021-07-01

申请号：US17181485

申请日：2021-02-22

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Luigi Colombo ,  Haowen Bu

IPC: H01L49/02 ,  H01L21/02 ,  H01L27/06 ,  H01G4/08 ,  H01L29/06

Abstract: In a described example, an integrated circuit includes a capacitor first plate; a dielectric stack over the capacitor first plate comprising silicon nitride and silicon dioxide with a capacitance quadratic voltage coefficient less than 0.5 ppm/V2; and a capacitor second plate over the dielectric stack.

公开(公告)号：US10665663B1

公开(公告)日：2020-05-26

申请号：US16198527

申请日：2018-11-21

Applicant: Texas Instruments Incorporated

Inventor： Poornika Fernandes ,  Bhaskar Srinivasan ,  Guruvayurappan Mathur ,  Abbas Ali ,  David Matthew Curran ,  Neil L. Gardner

IPC: H01L29/00 ,  H01L49/02 ,  H01L27/06 ,  H01L21/02 ,  H01L21/762 ,  H01L21/285 ,  H01L21/3213

Abstract: An integrated circuit (IC) includes a semiconductor surface layer on a substrate including functional circuitry having circuit elements configured together with a metal-to-polysilicon capacitor on the semiconductor surface layer for realizing at least one circuit function. The metal-to-polysilicon capacitor includes a bottom plate including polysilicon, a capacitor dielectric including at least one capacitor dielectric layer on the bottom plate, a top plate on the capacitor dielectric, and contacts through a pre-metal dielectric layer that contact the top plate and contact the bottom plate. In lateral regions relative to the capacitor the capacitor dielectric layer has a thickness in a range between about 5% and about 50% of a thickness of the capacitor dielectric of the metal-to-polysilicon capacitor.